library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fifo_code is
port(datain: in std_logic_vector(7 downto 0);
push : in std_logic;
pop : in std_logic;
reset : in std_logic;
clk : in std_logic;
full : out std_logic;
empty : out std_logic;
dataout:out std_logic_vector(7 downto 0));
end fifo_code;
architecture Behavioral of fifo_code is
type arraylogic is array(15 downto 0) of std_logic_vector(7 downto 0);
signal data:arraylogic;
signal fi:std_logic;
signal ei:std_logic;
signal wp,rp,a:integer range 0 to 15;
begin
process(clk,reset)
begin
if reset='1' then
wp<=0;
rp<=0;
dataout<=(others=>'0');
for i in 0 to 15 loop
data(i)<="00000000";
end loop;
elsif clk'event and clk='1' then
if (fi='0' and push='1' and wp<15) then
data(wp)<=datain;
wp<=wp+1;
end if;
if (fi='0' and push='1' and wp=15) then
data(wp)<=datain;
wp<=0;
end if;
if(ei='0' and pop='1' and rp<15) then
dataout<=data(rp);
rp<=rp+1;
end if;
if(ei='0' and pop='1' and rp=15) then
dataout<=data(rp);
rp<=0;
end if;
end if;
end process;
process(clk,reset)
begin
if reset='1' then
fi<='0';
ei<='1';
a<=0;
elsif clk'event and clk='1' then
if(pop='1' and a>0) then
a<=a-1;
fi<='0';
end if;
if (push='1'and a<15) then
a<=a+1;
ei<='0';
end if;
if a=0 then
ei<='1';
else ei<='0';
end if;
if a=15 then
fi<='1';
else
fi<='0';
end if;
end if;
end process;
full<=fi;
empty<=ei;
end Behavioral;
不能同时读写，如何改进哪呢过同时正确读写呢？谢谢 |
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