同一个BANK,LVDS和其他IO共存

发表于 2011-3-19 00:13

关于一个bank，lvds和非lvds共存，它们的比例关系和数量有什么要求。

发表于 2011-3-19 00:13

 Spartan-6 FPGA GTP Transceiver - SelectIO to GTP Crosstalk/SSO Guidelines
Description
Testing has shown that the GTP Transceivers in the Spartan-6 FPGAs can show a susceptibility to activity on adjacent SelectIO banks. As a result, Xilinx has updated its recommendations for utilizing pins in banks 0 and 2. This Answer Record contains early recommendations for SelectIO usage to minimize aggression onto the GTP Transceivers.

发表于 2011-3-19 00:13

Solution

The Spartan-6 FPGA GTP Transceivers can be located at the top and bottom of the die. Devices with 1 or 2 GTPA1_DUALs have them located at the top, while devices with 4 GTPA1_DUALs have them at both the top and the bottom of the device. Those transceivers located at the top of the device are adjacent to the SelectIO bank 0 while transceivers at the bottom are adjacent to bank 2. From a GTP naming perspective, MGT101 and MGT123 are both adjacent to bank 0, and MGT245 and MGT267 are both adjacent to bank 2.

To minimize the impact to GTP performance from SelectIO in an adjacent bank, the following recommendations should be followed and have been sorted by package.

发表于 2011-3-19 00:14

FG(G)484: Additional Guidelines only if 3.3V standards are being used

If no 3.3V I/O standards are being used in bank 0 (bank 2 is irrelevant as none of the devices use GTPs in this bank), there are no additional guidelines beyond the SSO Guidelines in the Spartan-6 FPGA Data Sheet (DS162). If 3.3V I/O standards are going to be used in bank 0 with VCCO set to 3.3V, the weighting in the table below can be used to calculate the number of I/O that can be used. Multiplying the number of I/O in each category by its weight then adding them together cannot exceed 92 in banks adjacent to GTP Transceivers used in the design.

I/O Weightings for the FG(G)484 Package:
I/O Category Weight
Single Ended Output    4
Single Ended Input    2
Differential Input/Output Pins    1

发表于 2011-3-19 00:14

LX150T-FG(G)676: Avoid Pins and additional guidelines

To avoid excess impact to performance to the GTP Transceivers, certain pins should not be used for toggling I/O. The following ranges define a rectangle of pins that should be avoided. For the purpose of these calculations, GCLK pins should be treated as inputs.
Bank 0:
 Rows A to K
 Columns 11 to 15
Bank 2:
 Rows U to AF
 Columns 12 to 16

发表于 2011-3-19 00:15

I/O Weightings for the LX150T-FG(G)676 and LX75T-FG(G)676

The maximum number of I/O that can be used in each bank are most strongly influenced by the voltage of the I/O standard used.  This section is broken up between 3.3V standards and 2.5V and less standards.

For I/O standards operating at or below 2.5V, the weights in the table below can be used to calculate the maximum number of each type of I/O that can be used in banks 0 when MGTs 101 or 123 are used or bank 2 when MGTs 245 or 267 are used. Multiplying the number of I/O in each category by its weight then adding them together cannot exceed 80 in banks adjacent to GTP Transceivers used in the design.
I/O Category Weight
Single Ended Output    4
Single Ended Input    2
Differential Input/Output Pins    1

For 3.3V I/O standards, guidelines for banks 0 and 2 can be found below and utilize the same 80 point maximum. For 3.3V Strong outputs (>4mA), a maximum of 100 pins can be used in the side banks, banks 1, 3, 4 and 5 (these banks have no limits for weak 3.3V or less I/O other than the SSO limits in the Spartan-6 FPGA Data Sheet (DS162).

Bank0:
I/O Category    Weight
Single Ended Strong Output (>4mA)    Not Permitted
Single Ended Weak Output (4mA)    16
Single Ended Strong Input (>4mA)    Not Permitted
Single Ended Weak Inputs (4mA)    8

Bank2:
I/O Category    Weight
Single Ended Strong Output (>4mA)    4
Single Ended Weak Output (4mA)    3.2
Single Ended Strong Input (>4mA)    2
Single Ended Weak Inputs (4mA)    1.6

发表于 2011-3-19 00:15

LX100T-FG(G)676: Avoid Pins and additional guidelines

To avoid excess impact to performance to the GTP Transceivers, certain pins should not be used for toggling I/O. The following ranges define a rectangle of pins that should be avoided. For the purpose of these calculations, GCLK pins should be treated as inputs.
Bank 0:
 Rows A to K
 Columns 11 to 15
Bank 2:
 Rows U to AF
 Columns 12 to 16
In addition, the weights in the table below can be used to calculate the maximum number of each type of I/O that can be used. Multiplying the number of I/O in each category by its weight then adding them together cannot exceed 80 in banks adjacent to GTP Transceivers used in the design. These weights are only dependent on I/O type and strength and are independent of I/O voltage.

发表于 2011-3-19 00:15

I/O Weightings for the LX100T-FG(G)676:

Bank0: Maximum = 80
I/O Category    Weight
Single Ended Strong Output (>4mA)    4
Single Ended Weak Output (4mA)    2.7
Single Ended Strong Input (>4mA)    2
Single Ended Weak Inputs (4mA)    1.3
Differential Output Pins    1
Differential Input Pins    0

Bank2: Maximum = 60
I/O Category    Weight
Single Ended Strong Output (>4mA)    4
Single Ended Weak Output (4mA)    2.4
Single Ended Strong Input (>4mA)    2
Single Ended Weak Inputs (4mA)    1.2
Differential Output Pins    1
Differential Input Pins    0

发表于 2011-3-19 00:15

Additional suggestions for optimal performance in FG(G)676 packages:
Start utilizing pins on the sides of the bank first, moving inward.
Reduce the drive strength and slew rate as much as possible.
Utilize the local reference clock inputs if possible rather than routing clocks from adjacent GTPA1_DUALs.

发表于 2011-3-19 00:16

Additional suggestions for optimal performance in FG(G)900:
Start utilizing pins on the sides of the bank first, moving inward.
Reduce the drive strength and slew rate as much as possible.
Prioritize the use of MGT101 and MGT245, GTPA1_X0Y1 and GTPA1_X0Y0.
Utilize the local reference clock inputs if possible rather than routing clocks from adjacent GTPA1_DUALs.

发表于 2011-3-19 00:16

Other Spartan-6 Packages: CSG324 and CSG484:
Limit of 20 pins in banks 0 and 2 (where GTPs are used).
20 pins do not include static or LVDS inputs/outputs.
Avoid high drive strength I/O standards on banks 0 and 2.
No additional limits on side banks/GCLKs. Refer to the Spartan-6 FPGA Data Sheet (DS162) for SSO Guidelines:
http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf

发表于 2011-3-20 21:48

:handshake

发表于 2011-6-22 22:31

E文，:Q先留个印。

[matlab] 同一个BANK,LVDS和其他IO共存

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