我们先看一下TI手册中关于I2C的使用（如AM3517为 http://focus.ti.com.cn/cn/lit/ug/sprugr0b/sprugr0b.pdf）
15.5.1.1.1 Configure the Module Before Enabling the I2C Controller
在使能I2C控制器之前配置整个I2C功能模块
Before enabling the I2C controller, perform the following steps: 在使能I2C控制器之前，完成如下操作
1. Enable the functional and interface clocks (see Section 15.3.1.1.1). 使能功能及接口时钟（参考15.3.1.1.1节）
2. Program the prescaler to obtain an approximately 12-MHz internal sampling clock (I2Ci_INTERNAL_CLK) by programming the corresponding value in the I2Ci.I2C_PSC[3:0] PSC field. This value depends on the frequency of the functional clock (I2Ci_FCLK). Because this frequency is 96MHz, the I2Ci.I2C_PSC[7:0] PSC field value is 0x7.
配置预分频器I2Ci.I2C_PSC[3:0]以获得大约12MHz的内部采样时钟（I2Ci_INTERNAL_CLK）. 相应的参数值依赖于功能时钟（I2Ci_FCLK）的频率。如当此时钟为96MHz时，则I2Ci.I2C_PSC[7:0] 可设为0x7
3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH fields to obtain a bit rate of 100K bps or 400K bps. These values depend on the internal sampling clock frequency (see Table 15-12).
设置I2Ci.I2C_SCLL[7:0] SCLL 及I2Ci.I2C_SCLH[7:0] SCLH 域以获得100K bps或是400K bps的波特率。这两个值依赖于内部采样时钟（参考表15-12)
4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of 400K bps or 3.4M bps (for the second phase of HS mode). These values depend on
the internal sampling clock frequency (see Table 15-12). 可选的设置，当需要使用高I2C总线时需要设置
5. (Optional) If a bit rate of 3.4M bps is used and the bus line capacitance exceeds 45 pF, program the CONTROL.CONTROL_DEVCONF1[12] I2C1HSMASTER bit for I2C1, the CONTROL.CONTROL_DEVCONF1[13] I2C2HSMASTER bit for I2C2, or the CONTROL.CONTROL_DEVCONF1[14] I2C3HSMASTER bit for I2C3. 可选的设置，当需要使用高I2C总线时需要设置
6. Configure the Own Address of the I2C controller by storing it in the I2Ci.I2C_OA0 register. Up to four Own Addresses can be programmed in the I2Ci.I2C_OAi registers (with i = 0, 1, 2, 3) for each I2C controller.
NOTE: For a 10-bit address, set the corresponding expand Own Address bit in the I2Ci.I2C_CON register.
设置 I2Ci.I2C_OAi 寄存器，配置CPU的I2C控制器的地址，每个I2C控制器共可配置４个地址即I2C_OAi中的i可取值０、１、２、３.
注： 对于10位地址，还需要设置每个控制器的对应I2Ci.I2C_CON寄存器
7. Set the TX threshold (in transmitter mode) and the RX threshold (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX threshold - 1), where the TX and RX thresholds are greater than or equal to 1.
设置TX门限及RX门限，I2Ci.I2C_BUF[5:0]XTRSH 域为(TX门限-1) , I2Ci.I2C_BUF[13:8]RTRSH 域为（RX门限-1）, TX门限及RX门限大于或等于１.
8. Take the I2C controller out of reset by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1.
设置 I2Ci.I2C_CON[15] I2C_EN位来启动I2C控制器
15.5.1.1.2 Initialize the I2C Controller
初始化I2C控制器
To initialize the I2C controller, perform the following steps:
要初始化I2C控制器，操作如下：
1. Configure the I2Ci.I2C_CON register:
配置 I2Ci.I2C_CON 寄存器
• For master or slave mode, set the I2Ci.I2C_CON[10] MST bit (0: slave, 1: master).
主从模式由 I2Ci.I2C_CON[10] MST位决定， ０表示从模式，１表示主模式
• For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX bit (0: receiver, 1: transmitter).
发送器还是接受器，由I2Ci.I2C_CON[9] TRX 位决定，０表示接收器，１表示发送器。
2. If using an interrupt to transmit/receive data, set to 1 the corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4] XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY bit for the receive
interrupt). （对于RTC功能模组，不需要使用中断来进行数据传输）
3. If using DMA to receive/transmit data, set to 1 the corresponding bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit for
the transmit DMA channel).（对于RTC功能模组，不需要使用DMA来进行数据了传输）
15.5.1.1.3 Configure Slave Address and the Data Control Register
配置从地址及数据控制寄存器
In master mode, configure the slave address register by programming the I2Ci.I2C_SA[9:0] SA field and the number of data bytes (I2C data payload) associated with the transfer by programming the I2Ci.I2C_CNT[15:0] DCOUNT field.
在主模式下，通过I2Ci.I2C_SA[9:0] SA域来写人要访问的从设备的地址，及通I2Ci.I2C_CNT[15:0] DCOUNT 域来设置一次要传输的字节数，
15.5.1.1.4 Initiate a Transfer
发起一次传输
Poll the I2Ci.I2C_STAT[12] BB bit. If it is cleared to 0 (bus not busy), configure the I2Ci.I2C_CON[0] STT and I2Ci.I2C_CON[1] STP bits. To initiate a transfer, the I2Ci.I2C_CON[0] STT bit must be set to 1, and it is not mandatory to set the I2Ci.I2C_CON[1] STP bit to 1.
查询 I2Ci.I2C_STAT[12] BB 位，如果该位为0（总线不忙），则配置I2Ci.I2C_CON[0] STT and I2Ci.I2C_CON[1] STP位，STT位必须设为1,STP并不强制一定为1.
15.5.1.1.5 Receive Data
接收数据
Poll the I2Ci.I2C_STAT[3] RRDY bit, or use the RRDY interrupt (the I2Ci.I2C_IE[3] RRDY_IE bit must be set to 1) or the DMA RX channel (the I2Ci.I2C_BUF[15] RDMA_EN bit must be set to 1) to read the receive data in the I2Ci.I2C_DATA register.
查询I2Ci.I2C_STAT[3] RRDY位，或使用RRDY中断（I2Ci.I2C_IE[3] RRDY_IE位须设为1）或DMA RX通道（ I2Ci.I2C_BUF[15] RDMA_EN位必须设为1）来从I2Ci.I2C_DATA寄存器读取数据
If the transfer length does not equal the RX FIFO threshold (I2Ci.I2C_BUF[13:8]RTRSH field + 1), use the draining feature (enable the RDR interrupt by setting the I2Ci.I2C_IE[13] RDR_IE bit to 1).
如果传输长度不等于RX FIFO门限(I2Ci.I2C_BUF[13:8]RTRSH 域 + 1), 则使用draining功能（设置 I2Ci.I2C_IE[13] RDR_IE 位为1,使能RDR中断）
NOTE: In receive mode only, the I2Ci.I2C_STAT[11] ROVR (receive overrun) bit indicates whether the receiver has experienced overrun. An overrun condition occurs when the shift register and the RX FIFO are full. An overrun condition does not result in data loss; the I2C controller simply holds the serial clock line i2ci_scl to low to prevent other bytes from being received. The I2Ci.I2C_STAT[7] AERR bit is set to 1 when a read access is performed in the
I2Ci.I2C_DATA register while the RX FIFO is empty. The corresponding interrupt can be enabled by setting the I2Ci.I2C_IE[7] AERR_IE bit to 1.
注：仅用于接收器模式， I2Ci.I2C_STAT[11] ROVR 位指示着接收器是否超载，超载表示移位寄存器及RX FIFO已满，但并不会导致数据丢失，这时I2C控制器将置I2Ci_SCL为低电平，来限制接收其余字节。当RX FIFO为空时，当RX FIFO为空时，读I2Ci.I2C_DATA寄存器，将导致I2Ci.I2C_STAT[7] AERR位为1. 相应的中断可以通过设置I2Ci.I2C_IE[7]为1来使能。
15.5.1.1.6 Transmit Data
发送数据
Poll the I2Ci.I2C_STAT[4] XRDY bit, or use the XRDY interrupt (the I2Ci.I2C_IE[4] XRDY_IE bit must be set to 1) or the DMA TX channel (the I2Ci.I2C_BUF[7] XDMA_EN bit must be set to 1) to write data to the
I2Ci.I2C_DATA register.
查询I2Ci.I2C_STAT[4] XRDY 位，或使用XRDY中断（I2Ci.I2C_IE[4] XRDY_IE 须设为1）或DMA TX通道（I2Ci.I2C_BUF[7] XDMA_EN 位须设为1），写数据到I2Ci.I2C_DATA寄存器。
If the transfer length does not equal the TX FIFO threshold (I2Ci.I2C_BUF[5:0] XTRSH field + 1), use the draining feature (enable the XDR interrupt by setting the I2Ci.I2C_IE[14] XDR_IE bit to 1).
如果发送长度不等于TX FIFO门限（I2Ci.I2C_BUF[5:0] XTRSH field + 1），可使用draining功能（设置 I2Ci.I2C_IE[14]XDR_IE 位为1,使能XDR中断）
NOTE: In transmit mode only, the I2Ci.I2C_STAT[10] XUDF bit indicates whether the transmitter has experienced underflow.
注：仅用于发送器模式，I2Ci.I2C_STAT[10] XUDF 位指示发送器是否欠载。
In master transmit mode, underflow occurs when the shift register and the TX FIFO are empty and there are still some bytes to transmit (the I2Ci.I2C_CNT[15:0] DCOUNT field value is not 0).
在主发送器模式， 欠载出现于当仍有部分字节需要传输（I2Ci.I2C_CNT[15:0] DCOUNT 位不为0）时移位寄存器及TX FIFO为空。
In slave transmit mode, underflow occurs when the shift register and the TX FIFO are empty and the external I2C master device still requests data bytes to be read. The I2Ci.I2C_STAT[7] AERR bit is set to 1 when a write access is performed in the I2Ci.I2C_DATA register while the TX FIFO is full. The corresponding interrupt can be enabled by setting the I2Ci.I2C_IE[7] AERR_IE bit to 1.
在从发送器模式，欠载出现于，当外部主I2C器件仍处于请求读取数据时移位寄存器及TX FIFO为空。当TX FIFO全满时，写I2Ci.I2C_DATA寄存器将导致I2Ci.I2C_STAT[7] AERR位被置1。可以通过设I2Ci.I2C_IE[7] AERR_IE 位为1来使能相应的中断。 |
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