先上程序：
module ht1621
(
input clk,
input rst_n,
output reg sdio,
output reg sclk,
output reg stb
);
reg [15:0] olddata;
reg [4:0] currentstate;
parameter s1 = 5'b0_0001;
parameter s2 = 5'b0_0010;//设置工作模式
parameter s3 = 5'b0_0011;
parameter s4 = 5'b0_0100;//固定地址写数据
parameter s5 = 5'b0_0101;//
parameter s6 = 5'b0_0110;//S6和S5状态设置扫描限值寄存器
parameter s7 = 4'b0_0111;//
parameter s8 = 5'b0_1000; //S7和S8状态 设置正常显示模式
parameter s10 =5'b0_1010;//
parameter s11 =5'b0_1011;//s10和是1状态 送入显示的数据
parameter Init=5'b1_1110;
parameter Init1=5'b1_1111;
reg [5:0]counter;
parameter
seg1 = 16'h14ab,
seg2 = 16'h14bc,
seg3 = 16'h14cd, //1.
seg4 = 16'h14de, //2
seg5 = 16'h14ef, //3
seg6 = 16'h14ff; //4
reg [2:0]cnt;
//产生时钟
always @(posedge clk)
begin
if(!rst_n) begin
counter<=6'd0;
sclk <= 1'b1;
end
else begin
if(counter==6'd32) begin
sclk <= ~sclk;
counter<=6'd0;
end
else counter<=counter+6'd1;
end
end
reg [3:0] sclk_cnt;//同步时钟计数器，15
always @(posedge sclk or negedge rst_n)
begin
if(!rst_n) sclk_cnt <= 1'b0;
else
case(currentstate)
Init1,s2,s4,s6,s8,s11:
if(4'd15 == sclk_cnt)
sclk_cnt <= 1'b0;
else sclk_cnt <= sclk_cnt + 1'b1;
default: sclk_cnt <= 1'b0;
endcase
end
reg [15:0] data;
//主状态机
always @(posedge sclk or negedge rst_n)
begin
if(!rst_n) begin currentstate <=Init; cnt = 3'b0; end
else
case(currentstate)
Init:currentstate <=Init1;
Init1:begin
if(4'd15 == sclk_cnt) //16个时钟周期将数据送出去
currentstate <= s7;
else
currentstate <= Init1;
end
s1: currentstate <= s2; //s1和S2状态设置译码寄存器
s2:begin
if(4'd15 == sclk_cnt) //16个时钟周期将数据送出去
currentstate <= s3;
else
currentstate <= s2;
end
s3: currentstate <= s4;//S3和S4状态设置亮度寄存器
s4: begin
if(4'd15 == sclk_cnt) //16个时钟周期将数据送出去
currentstate <= s5;
else
currentstate <= s4;
end
s5: currentstate <= s6;// S6和S5状态设置扫描限值寄存器
s6: begin
if(4'd15 == sclk_cnt) //16个时钟周期将数据送出去
currentstate <= s10;
else
currentstate <= s6;
end
s7: currentstate <= s8;// S7和S8状态 设置正常显示模式
s8: begin
if(4'd15 == sclk_cnt) //16个时钟周期将数据送出去
currentstate <= s1;
else
currentstate <= s8;
end
//初始化完成
s10: if(olddata != data)
currentstate <= s11;// 正常送数据显示
else
currentstate <= s10;
s11: begin
if(4'd15 == sclk_cnt) //16个时钟周期将数据送出去
begin
currentstate <= s10;
cnt = cnt + 1'b1;
end
else
currentstate <= s11;
end
endcase
end
always @(posedge sclk or negedge rst_n)
begin
if(!rst_n)begin data <= 16'h0000; olddata <= 16'h0000; end
else case(currentstate)
Init:data <= 16'h0852; //0b1000 0101 0010 1/3duty 4com
s7: data <= 16'h0830; //0b1000 0011 0000 内部时钟
s1: data <= 16'h080A; //0b1000 0000 1010 禁止看门狗
s3: data <= 16'h0802; //0b1000 0000 0010 打开系统振荡器
s5: data <= 16'h0806; //0b1000 0000 0110 打开LCD偏压
s10: begin
case(cnt)
3'd0: data <= seg1;
3'd1: data <= seg2;
3'd2: data <= seg3;
3'd3: data <= seg4;
3'd4: data <= seg5;
3'd5: data <= seg6;
endcase
olddata <= data;
end//{4'b0000,dd,4'b000,dd};olddata <=16'h0c01;end//{4'b0000,4'd4,8'd6};olddata <= {4'b0000,4'd4,8'd6};;;end//16'h080e; //待显示的数据
Init1,s2,s4,s6,s8,s11: begin data <= data << 1; olddata <= olddata; end//循环移位 将高位送出
default: begin data <= 16'h0000; olddata <= olddata; end
endcase
end
//----------数据串行---------
always @(posedge sclk or negedge rst_n)
begin
if(!rst_n) sdio <= 1'b0;
else case(currentstate)
Init1,s2,s4,s6,s8,s11: sdio <= data[15];
default: sdio <= 1'b0;
endcase
end
//----------串行数据写有效LOAD----------
always @(posedge sclk or negedge rst_n)
begin
if(!rst_n) stb <= 1'b1;
else case(currentstate)
Init1,s2,s4,s6,s8,s11: stb <= 1'b0; //送数的时候处于低
default: stb <= 1'b1; //非送数时候，拉高 锁存数据
endcase
end
endmodule
可是下载到板子里，液晶一段也不亮。
请高手看看，哪里有问题。谢谢！
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