signal OUT_A: std_logic;
signal INBUF: std_logic_vector(0 to 1);
process(CLK)
begin
if CLK'event and CLK = '1' then
INBUF(0) <= IN_PIN;
INBUF(1) <= INBUF(0);
end if;
end process;
process(CLK)
variable CNT3: integer range 0 to 3;
begin
if CLK'event and CLK = '1' then
if INBUF(0) = '1' and INBUF(1) = '0' then --IN上升沿
OUT_A <= '1';
CNT3 := CNT3 + 1;
end if;
if CNT3 = 3 then
CNT3 := 0;
OUT_A <= '0';
end if;
OUT_PIN <= OUT_A or INBUF(0);
end if;
end process;
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