如何设置自动FIFO，能在总线上探测到CBW信号？

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yp19890718| 实习生

楼主 | 2012-3-29 14:38 | 只看该作者回帖奖励

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FIFO, 信号, 总线, CD, se

先贴上程序
void TD_Init(void)          // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
IFCONFIG |= 0x02;//异步，从FIFO模式.
PORTACFG |= 0x00;//选择SLCSA功能脚。
FIFOPINPOLAR = 0x00; // set all slave FIFO interface pins as active low PKTEND OR SLOE SLWR LOW AVTIVE
SYNCDELAY;
REVCTL = 0x03; // enable the external master
SYNCDELAY;
//reset the fifos
  FIFORESET = 0x80;
  SYNCDELAY;
  FIFORESET = 0x02;
  SYNCDELAY;
  FIFORESET = 0x04;
  SYNCDELAY;
  FIFORESET = 0x06;
  SYNCDELAY;
  FIFORESET = 0x08;
  SYNCDELAY;
  FIFORESET = 0x00;
  SYNCDELAY;
  //fix the slave fifo flags, only flagb and flagc
  //PINFLAGSAB = 0x89;  //F,FLAGB IS THE FIFO2 EMPTY FLAG,LAGA IS THE FIFO4 EMPTY FLAG
  //SYNCDELAY;
  PINFLAGSAB = 0xBE;  //FLAGC IS THE FIFO6 FULL  FLAG
  SYNCDELAY;
  // config the endpoints direction
  EP1OUTCFG = 0xA0;//enable and bulk type
  EP1INCFG = 0xA0;
  /*SYNCDELAY;                   // see TRM section 15.14
  EP2CFG = 0xA2;
  SYNCDELAY;
  EP4CFG = 0xA2; */
  SYNCDELAY;
  EP6CFG = 0xe2;//enable IN bulk 512 DOUBLE buffer
  SYNCDELAY;
EP8CFG = 0xA2;
  SYNCDELAY;
  EP8FIFOCFG = 0x11;//EP2 IS AUTOOUT=1 AUTOIN =0 ZEROLEN=0 WORDIDE=1 配置EP6自动方式16位总
  SYNCDELAY;
  //config the endpoint6
  EP6FIFOCFG = 0x0D;//EP6 IS AUTOOUT=0 AUTOIN =1 ZEROLEN=1 WORDIDE=1 配置EP6自动方式16位总
  SYNCDELAY;
AUTOPTRSETUP |= 0x01;
SYNCDELAY;
  //-------------------------
  INPKTEND = 0x06;
  SYNCDELAY;
  INPKTEND = 0x06;
  SYNCDELAY;
OUTPKTEND = 0x08;
  SYNCDELAY;
  OUTPKTEND = 0x08;
  SYNCDELAY;
  //----------------------------------------
  EP6AUTOINLENH = 0x02; //set the packet size 512
  SYNCDELAY;
  EP6AUTOINLENL = 0x00;
  SYNCDELAY;
            // arm EP2OUT by writing byte count w/skip.
// SYNCDELAY;
  // since the defaults are double buffered we must write dummy byte counts twice
  //SYNCDELAY;
  /*EP2BCL = 0x80;             // arm EP2OUT by writing byte count w/skip.
  SYNCDELAY;
  EP2BCL = 0x80;
  SYNCDELAY;          */
  EP8BCL = 0x80;             // arm EP8OUT by writing byte count w/skip.
  SYNCDELAY;
  EP8BCL = 0x80;
  SYNCDELAY;
  Rwuen = TRUE;
}

问题：
这是设置FIFO为自动型，EP8为自动OUT，EP6为自动IN。外接FPGA，设置好了相关接口描述符。本意是PC发数据到68013的FIFO然后到FPGA，用BUS HOUND查看EP1处理完后就不能转到EP8（OUT）发数据了，最终是自动RSET。不晓得哪里出问题了。求解释，哪里错了，还是哪里不周全。我在做U盘控制器，PC通过68013的FIFO发送CBW命令给FPGA，可惜总线上探测不到数据OUT。为什么？

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如何设置自动FIFO，能在总线上探测到CBW信号？

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