本帖最后由 dongly 于 2022-5-4 22:17 编辑
- 状况: AT32F407VGT7 用外部晶振25MHz时串口输出乱码
- 硬件: 晶振为25MHz无源晶振
- 标准库:V2.0.9
- 时钟配置: New Clock Configuration V2.00.06
- 例程: AT32F403A_407_Firmware_Library_V2.0.9\project\at_start_f407\examples\usart\printf
- 编译器信息
IDE-Version:
μVision V5.30.0.0
Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
Tool Version Numbers:
Toolchain: MDK-ARM Plus Version: 5.30.0.0
Toolchain Path: e:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.30.0.0
Dialog DLL: TCM.DLL V1.42.0.0
Target DLL: Segger\JL2CM3.dll V2.99.38.0
Dialog DLL: TCM.DLL V1.42.0.0
- 使用内部时钟HICK时,生成新的system_clock_config()替换原来的system_clock_config(),串口打印正常
/**
* [url=home.php?mod=space&uid=247401]@brief[/url] system clock config program
* [url=home.php?mod=space&uid=536309]@NOTE[/url] the system clock is configured as follow:
* - system clock = hick / 12 * pll_mult
* - system clock source = pll (hick)
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000
* - apb1div = 2
* - apb1clk = 120000000
* - apb2div = 2
* - apb2clk = 120000000
* - pll_mult = 60
* - pll_range = GT72MHZ (greater than 72 mhz)
* @param none
* @retval none
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable hick */
crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE);
/* wait till hick is ready */
while(crm_flag_get(CRM_HICK_STABLE_FLAG) != SET)
{
}
/* config pll clock resource */
crm_pll_config(CRM_PLL_SOURCE_HICK, CRM_PLL_MULT_60, CRM_PLL_OUTPUT_RANGE_GT72MHZ);
/* enable pll */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
/* wait till pll is ready */
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
{
}
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk */
crm_apb1_div_set(CRM_APB1_DIV_2);
/* enable auto step mode */
crm_auto_step_mode_enable(TRUE);
/* select pll as system clock source */
crm_sysclk_switch(CRM_SCLK_PLL);
/* wait till pll is used as system clock source */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
{
}
/* disable auto step mode */
crm_auto_step_mode_enable(FALSE);
/* update system_core_clock global variable */
system_core_clock_update();
}
- 在PA8输出sclk的64分频(理论值3.750MHz)为3.760MHz
- 使用外部晶振时,生成新的system_clock_config(),串口打死乱码(用分析仪查看了一下,貌似波特率不对)
/**
* [url=home.php?mod=space&uid=247401]@brief[/url] system clock config program
* [url=home.php?mod=space&uid=536309]@NOTE[/url] the system clock is configured as follow:
* - system clock = hext / 5 * pll_mult
* - system clock source = pll (hext)
* - hext = 25000000
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000
* - apb1div = 2
* - apb1clk = 120000000
* - apb2div = 2
* - apb2clk = 120000000
* - pll_mult = 48
* - pll_range = GT72MHZ (greater than 72 mhz)
* @param none
* @retval none
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable hext */
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */
while(crm_hext_stable_wait() == ERROR)
{
}
/* config pll clock resource */
crm_pll_config(CRM_PLL_SOURCE_HEXT_DIV, CRM_PLL_MULT_48, CRM_PLL_OUTPUT_RANGE_GT72MHZ);
/* config hext division */
crm_hext_clock_div_set(CRM_HEXT_DIV_5);
/* enable pll */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
/* wait till pll is ready */
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
{
}
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk */
crm_apb1_div_set(CRM_APB1_DIV_2);
/* enable auto step mode */
crm_auto_step_mode_enable(TRUE);
/* select pll as system clock source */
crm_sysclk_switch(CRM_SCLK_PLL);
/* wait till pll is used as system clock source */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
{
}
/* disable auto step mode */
crm_auto_step_mode_enable(FALSE);
/* update system_core_clock global variable */
system_core_clock_update();
}
- 在PA8输出sclk的64分频(理论值3.750MHz)为3.751MHz,说明时钟是正常的
请问各位大能,这个问题出哪里?
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