本帖最后由 叶萌 于 2022-10-24 17:48 编辑
定时器1和定时器4设置为主从模式,为何不行,请大佬帮我看看?定时器1PWM输出
3mhz的方波,然后同时可以触发定时器4生成5khz的中断。代码如下:
void InitTime1Config(void)
{
GPIO_Config_T GPIO_ConfigStruct;
TMR_BaseConfig_T TMR_TimeBaseStruct;
TMR_OCConfig_T OCcongigStruct;
RCM_EnableAPB2PeriphClock((RCM_APB2_PERIPH_T)(RCM_APB2_PERIPH_GPIOA | RCM_APB2_PERIPH_TMR1 ));
GPIO_ConfigStruct.pin = GPIO_PIN_8;
GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP;
GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
GPIO_Config(GPIOA, &GPIO_ConfigStruct);
TMR_TimeBaseStruct.clockDivision = TMR_CLOCK_DIV_1;
TMR_TimeBaseStruct.countMode = TMR_COUNTER_MODE_UP;
TMR_TimeBaseStruct.division = 0;
TMR_TimeBaseStruct.period = 19;
TMR_ConfigTimeBase(TMR1, &TMR_TimeBaseStruct);
TMR_SelectSinglePulseMode(TMR1,TMR_SPM_SINGLE);
TMR_SelectSlaveMode(TMR1,TMR_SLAVE_MODE_TRIGGER);
TMR_EnableMasterSlaveMode(TMR1);
TMR_SelectOutputTrigger(TMR1,TMR_TRGO_SOURCE_UPDATE);
OCcongigStruct.idleState = TMR_OC_IDLE_STATE_RESET;
OCcongigStruct.mode = TMR_OC_MODE_PWM1;
OCcongigStruct.nIdleState = TMR_OC_NIDLE_STATE_RESET;
OCcongigStruct.nPolarity = TMR_OC_NPOLARITY_HIGH;
OCcongigStruct.outputNState = TMR_OC_NSTATE_DISABLE;
OCcongigStruct.outputState = TMR_OC_STATE_DISABLE;
OCcongigStruct.polarity = TMR_OC_POLARITY_LOW;
OCcongigStruct.pulse = 10;
TMR_ConfigOC1(TMR1, &OCcongigStruct);
TMR_ConfigOC1Preload(TMR1, TMR_OC_PRELOAD_ENABLE);
TMR_EnableAUTOReload(TMR1);
TMR_Enable(TMR1);
TMR_EnablePWMOutputs(TMR1);
}
void InitTime4Config(void)
{
TMR_BaseConfig_T TMR_BaseConfigStruct;
RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR4);
TMR_BaseConfigStruct.clockDivision = TMR_CLOCK_DIV_1;
TMR_BaseConfigStruct.countMode = TMR_COUNTER_MODE_UP;
TMR_BaseConfigStruct.division = 29;
TMR_BaseConfigStruct.period = 9;
TMR_BaseConfigStruct.repetitionCounter = 0;
TMR_ConfigTimeBase(TMR4, &TMR_BaseConfigStruct);
TMR_SelectSlaveMode(TMR4,TMR_SLAVE_MODE_EXTERNALL);
TMR_EnableMasterSlaveMode(TMR4);
TMR_SelectInputTrigger(TMR4,TMR_TRIGGER_SOURCE_ITR0);
TMR_EnableInterrupt(TMR4, TMR_INT_UPDATE);
NVIC_EnableIRQRequest(TMR4_IRQn, 0, 0);
TMR_Enable(TMR4);
}
|