module ppblaze(clk,rst,port_id,out_port);
/***** *****/
input clk,rst;
output[7:0] port_id;
output[7:0] out_port;
//--- ---
wire [9:0] address;
wire [17:0] instruction;
wire [5:0] cmd;//just for simulate
assign cmd = instruction[17:12];
/*** ***/
reg clk_div2;
always @(posedge clk or posedge rst) begin
if(rst) clk_div2 <= 1'd0;
else clk_div2 <= ~clk_div2;
end
/*** ****/
reg pc_sel,rs1_sel,rs1_load,id_load,out_load;
always @(rst or instruction) begin
if(rst) {pc_sel,rs1_sel,rs1_load,id_load,out_load} <= 5'b00000;
else
case (instruction[17:12])
6'b000000:{pc_sel,rs1_sel,rs1_load,id_load,out_load} <= 5'b00100;//load
6'b011000:{pc_sel,rs1_sel,rs1_load,id_load,out_load} <= 5'b01100;//add
6'b101100:{pc_sel,rs1_sel,rs1_load,id_load,out_load} <= 5'b00011;//out
6'b110100:{pc_sel,rs1_sel,rs1_load,id_load,out_load} <= 5'b10000;//jump
default:{pc_sel,rs1_sel,rs1_load,id_load,out_load} <= 5'b00000;
endcase
end
/*** pc control ***/
reg [9:0] pc_r;
always @(posedge clk_div2 or posedge rst) begin
if(rst) pc_r <= 10'd0;
else if(pc_sel) pc_r <= instruction[9:0];
else pc_r <= pc_r + 1'd1;
end
assign address = pc_r;
/*** rs1 regitor ***/
reg[7:0] rs1;
wire[7:0] rs1_data;
wire[7:0] add_reault;
assign rs1_data = rs1_sel ? add_reault:instruction[7:0];
always @(posedge clk_div2 or posedge rst) begin
if(rst) rs1 <= 8'd0;
else if(rs1_load) rs1 <= rs1_data;
end
/*** add ***/
assign add_reault = instruction[7:0] + rs1;
/*** out instrution ***/
reg[7:0] port_id;
reg[7:0] out_port;
always @(posedge clk_div2 or posedge rst) begin
if(rst) {port_id,out_port} <= {8'd0,8'd0};
else begin
if(id_load) port_id <= instruction[7:0];
if(out_load) out_port <= rs1;
end
end
/*** ***/
led program
(
.address(address),
.instruction(instruction),
.clk(clk));
endmodule
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