按照Xilinx提供的XPS实验做到Lab2时，编译出现了“ LOC constraint L13 on dip_GPIO_in_pin<0> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.”这个问题。
最终在Google上面搜索到了答案，总结如下：
网址：http://www.fpga-faq.com/archives/84675.html
This basically tells you that there is no pin "dip_GPIO_in_pin<0>" on your FPGA, which is understandable... Haven't seen any FPGAs with 130 rows/columns around lately :) You're trying to route he signal dig_video_out<3> to a pin that does not exist. Same with most of the other signals, your FPGA
can't possibly have pins like that. Check your pin assigments again.
看了看system.ucf发现，实验教材中使用的是spartan-3E的板子，而我使用的是Spartan 3A DSP1800A板子，原来在对管脚分配和定义时，把"dip_GPIO_in_pin<0>" 分配到了实际不存在的引脚，所以出现了这个错误。 改正管脚的名称后，再编译，ERROR没有了：） |
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