testbench文件如下
`timescale 1 ns/ 1 ns
module tri_bibuffer_test();
//port definition
reg en_t, wr_t, rd_t;
reg[7:0] data_in_t; //input data
wire[7:0] data_out_t, data_t; //output data
//module instantiated
tri_bibuffer i1
(
.data_bus(data_t),
.en(en_t),
.wr(wr_t),
.rd(rd_t)
);
//input and output control logic
assign data_t = ( rd_t & ~wr_t ) ? 8'bz : data_in_t; //data_t as a input port
assign data_out_t = ( rd_t & ~wr_t ) ? data_t : 8'bz; //data_t as a output port
//initialize the port
initial
begin
en_t = 1'b1;
wr_t = 1'b0;
rd_t = 1'b0;
data_in_t = 8'd0;
//CS is active
#100 en_t = 1'b0;
//data as a input, write datas to temp_data constantly
#100 wr_t = 1'b1;
#100 data_in_t = 8'd1;
#100 data_in_t = 8'd2;
#100 data_in_t = 8'd3;
#100 data_in_t = 8'd1;
#100 wr_t = 1'b0;
//data as a output, read datas from temp_data
#100 rd_t = 1'b1;
#100 rd_t = 1'b0;
//data as a input, write datas to temp_data 8'd3
#100 data_in_t = 8'd3;
#100 wr_t = 1'b1;
#100 wr_t = 1'b0;
//data as a output, read datas from temp_data 8'd3
#100 rd_t = 1'b1;
#100 rd_t = 1'b0;
//data as a input, write datas to temp_data 8'd2
#100 data_in_t = 8'd2;
#100 wr_t = 1'b1;
#100 wr_t = 1'b0;
//data as a output, read datas from temp_data 8'd2
#100 rd_t = 1'b1;
#100 rd_t = 1'b0;
//data as a input, write datas to temp_data 8'd0
#100 data_in_t = 8'd1;
#100 wr_t = 1'b1;
#100 wr_t = 1'b0;
//data as a output, read datas from temp_data 8'd0
#100 rd_t = 1'b1;
#100 rd_t = 1'b0;
//CS is not valid
#100 en_t = 1'b1;
#100 $stop;
end
endmodule
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