inout 双向数据口，前仿和门级仿真都通过了，时序仿真就是

只看该作者 · 2012-12-28 21:54

本帖最后由 zhpg009 于 2012-12-28 22:04 编辑

如题，错误如下

QuartusII 里面设置已经把Generate netlist for functional simulation only 设置成OFF

# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(167): Failed to find INSTANCE '\data_bus[0]~input '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(71): Failed to find INSTANCE '\data_bus[0]~output '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(44): Failed to find INSTANCE '\data_bus[1]~input '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(83): Failed to find INSTANCE '\data_bus[1]~output '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(305): Failed to find INSTANCE '\data_bus[2]~input '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(95): Failed to find INSTANCE '\data_bus[2]~output '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(342): Failed to find INSTANCE '\data_bus[3]~input '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(107): Failed to find INSTANCE '\data_bus[3]~output '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(379): Failed to find INSTANCE '\data_bus[4]~input '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(119): Failed to find INSTANCE '\data_bus[4]~output '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(53): Failed to find INSTANCE '\data_bus[5]~input '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(131): Failed to find INSTANCE '\data_bus[5]~output '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(444): Failed to find INSTANCE '\data_bus[6]~input '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(143): Failed to find INSTANCE '\data_bus[6]~output '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(62): Failed to find INSTANCE '\data_bus[7]~input '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(155): Failed to find INSTANCE '\data_bus[7]~output '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(240): Failed to find INSTANCE '\data_bus~16 '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(254): Failed to find INSTANCE '\data_bus~16clkctrl '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(194): Failed to find INSTANCE '\en~input '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(176): Failed to find INSTANCE '\rd~input '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(263): Failed to find INSTANCE '\reg_data[0] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(291): Failed to find INSTANCE '\reg_data[1] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(328): Failed to find INSTANCE '\reg_data[2] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(365): Failed to find INSTANCE '\reg_data[3] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(402): Failed to find INSTANCE '\reg_data[4] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(430): Failed to find INSTANCE '\reg_data[5] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(467): Failed to find INSTANCE '\reg_data[6] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(495): Failed to find INSTANCE '\reg_data[7] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(226): Failed to find INSTANCE '\temp_data[0] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(277): Failed to find INSTANCE '\temp_data[1] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(203): Failed to find INSTANCE '\temp_data[1]~0 '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(217): Failed to find INSTANCE '\temp_data[1]~0clkctrl '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(314): Failed to find INSTANCE '\temp_data[2] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(351): Failed to find INSTANCE '\temp_data[3] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(388): Failed to find INSTANCE '\temp_data[4] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(416): Failed to find INSTANCE '\temp_data[5] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(453): Failed to find INSTANCE '\temp_data[6] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(481): Failed to find INSTANCE '\temp_data[7] '.
#
# ** Error: (vsim-SDF-3250) E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo(185): Failed to find INSTANCE '\wr~input '.
#
# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).
#
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_v.sdo".
# Time: 0 ns Iteration: 0 Instance: /tri_bibuffer_test File: E:/Verilog_ex/exam_5/simulation/modelsim/Timing_sim/tri_bibuffer_test.v

求解释！

只看该作者 · 2012-12-28 21:58

testbench文件如下
`timescale 1 ns/ 1 ns
module tri_bibuffer_test();

  //port definition
  reg en_t, wr_t, rd_t;
  reg[7:0] data_in_t;          //input data
  wire[7:0] data_out_t, data_t; //output data

  //module instantiated
  tri_bibuffer i1
  (
.data_bus(data_t),
.en(en_t),
.wr(wr_t),
.rd(rd_t)
  );

  //input and output control logic
  assign data_t = ( rd_t & ~wr_t ) ? 8'bz : data_in_t;  //data_t as a input port
  assign data_out_t = ( rd_t & ~wr_t ) ? data_t : 8'bz;  //data_t as a output port

  //initialize the port
  initial
begin
   en_t = 1'b1;
   wr_t = 1'b0;
   rd_t = 1'b0;
   data_in_t = 8'd0;

   //CS is active
   #100 en_t = 1'b0;

   //data as a input, write datas to temp_data constantly
   #100 wr_t = 1'b1;
   #100 data_in_t = 8'd1;
   #100 data_in_t = 8'd2;
   #100 data_in_t = 8'd3;
   #100 data_in_t = 8'd1;
   #100 wr_t = 1'b0;

   //data as a output, read datas from temp_data
   #100 rd_t = 1'b1;
   #100 rd_t = 1'b0;

   //data as a input, write datas to temp_data 8'd3
   #100 data_in_t = 8'd3;
   #100 wr_t = 1'b1;
   #100 wr_t = 1'b0;

   //data as a output, read datas from temp_data 8'd3
   #100 rd_t = 1'b1;
   #100 rd_t = 1'b0;

   //data as a input, write datas to temp_data 8'd2
   #100 data_in_t = 8'd2;
   #100 wr_t = 1'b1;
   #100 wr_t = 1'b0;

   //data as a output, read datas from temp_data 8'd2
   #100 rd_t = 1'b1;
   #100 rd_t = 1'b0;

   //data as a input, write datas to temp_data 8'd0
   #100 data_in_t = 8'd1;
   #100 wr_t = 1'b1;
   #100 wr_t = 1'b0;

   //data as a output, read datas from temp_data 8'd0
   #100 rd_t = 1'b1;
   #100 rd_t = 1'b0;

   //CS is not valid
   #100 en_t = 1'b1;

   #100 $stop;
end

endmodule

只看该作者 · 2012-12-28 21:58

源文件如下：

module tri_bibuffer
(
data_bus, en, wr, rd
);

inout[7:0] data_bus;
input en, wr, rd;

reg[7:0] reg_data; //Image register,waiting for output
reg[7:0] temp_data; //Data input register

assign data_bus = ( ~en & rd & ~wr ) ? reg_data : 8'bz;

always @ ( en or wr or rd or temp_data or data_bus )
begin
if( ~en & rd & ~wr ) //output rd = 1
begin
reg_data = temp_data;
end
else if( ~en & ~rd & wr ) //input wr = 1
begin
temp_data = data_bus;
end
end

endmodule