module Divider_odd
#(parameter Divnum = 11)
(Reset,CLOCK_50,QCLK);
input Reset;
input CLOCK_50;
output reg QCLK;
reg [3:0] counter = 4'h0;
always @(posedge CLOCK_50,negedge Reset)
begin
if(!Reset)
counter <= 4'h0;
else if(counter >= 4'h5)
counter = 4'h0;
else counter = counter + 4'h1;
end
always @(negedge CLOCK_50,negedge Reset)
begin
if(!Reset)
QCLK <= 1'b1;
else QCLK <= counter[3];
end
endmodule
这段代码的编译结果中Total logic elements 1 / 33,216 ( < 1 % )
Total combinational functions 1 / 33,216 ( < 1 % )
Dedicated logic registers 1 / 33,216 ( < 1 % ) 怎么解决
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