第一次用FPGA，要用到GTP/GTX这块,看了一些资料但还是不知道怎么用，下面这个人做的跟我要做的一样，但是他的配置看不太懂，有谁帮忙分析分析，谢谢了
I'm using a virtex5 where i instantiated a rocket IO GTX.
In one hand i have an AD9239 ADC that send data at 4 Gbps and in another one my rocket IO that should receive data.
It s working but sometimes i have some problems with the comma alignment.
In a normal way i should have CC something every 4 packets of 4 bytes (CC is my comma value) :
- CC12 CD25 BB45 C548 CCD5 5478 EE87 F789 CC45 ...
but sometimes i have (1 extra packet):
- CC12 CD25 BB45 C548 C548 CCD5 5478 EE87 F789 CC45 ...
or (1 lost packet ):
- CC12 CD25 BB45 CCD5 5478 EE87 F789 CC45 ...
I don't know if my rocket IO settings are bad. Does someone can help me please ?
For infomation i put my rocket IO setting bellow :
##############################################################
#
# Xilinx Core Generator version 11.4
# Date: Thu Jan 06 15:36:09 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = True
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = True
SET designentry = VHDL
SET device = xc5vfx70t
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff665
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT RocketIO_GTX_Wizard family Xilinx,_Inc. 1.6
# END Select
# BEGIN Parameters
CSET cdr_ph_adj_time=01010
CSET component_name=rocketio_wrapper
CSET gtp0_bytes_to_reduce_error=8
CSET gtp0_cb_seq_1_1=00000000
CSET gtp0_cb_seq_1_1_disp=false
CSET gtp0_cb_seq_1_1_k=false
CSET gtp0_cb_seq_1_1_mask=true
CSET gtp0_cb_seq_1_2=00000000
CSET gtp0_cb_seq_1_2_disp=false
CSET gtp0_cb_seq_1_2_k=false
CSET gtp0_cb_seq_1_2_mask=true
CSET gtp0_cb_seq_1_3=00000000
CSET gtp0_cb_seq_1_3_disp=false
CSET gtp0_cb_seq_1_3_k=false
CSET gtp0_cb_seq_1_3_mask=true
CSET gtp0_cb_seq_1_4=00000000
CSET gtp0_cb_seq_1_4_disp=false
CSET gtp0_cb_seq_1_4_k=false
CSET gtp0_cb_seq_1_4_mask=true
CSET gtp0_cb_seq_2_1=00000000
CSET gtp0_cb_seq_2_1_disp=false
CSET gtp0_cb_seq_2_1_k=false
CSET gtp0_cb_seq_2_1_mask=true
CSET gtp0_cb_seq_2_2=00000000
CSET gtp0_cb_seq_2_2_disp=false
CSET gtp0_cb_seq_2_2_k=false
CSET gtp0_cb_seq_2_2_mask=true
CSET gtp0_cb_seq_2_3=00000000
CSET gtp0_cb_seq_2_3_disp=false
CSET gtp0_cb_seq_2_3_k=false
CSET gtp0_cb_seq_2_3_mask=true
CSET gtp0_cb_seq_2_4=00000000
CSET gtp0_cb_seq_2_4_disp=false
CSET gtp0_cb_seq_2_4_k=false
CSET gtp0_cb_seq_2_4_mask=true
CSET gtp0_cb_sequence_1_max_skew=1
CSET gtp0_cb_sequence_2_max_skew=1
CSET gtp0_cb_sequence_length=1
CSET gtp0_cc_keep_one_idle=false
CSET gtp0_cc_seq_1_1=00000000
CSET gtp0_cc_seq_1_1_disp=false
CSET gtp0_cc_seq_1_1_k=false
CSET gtp0_cc_seq_1_1_mask=true
CSET gtp0_cc_seq_1_2=00000000
CSET gtp0_cc_seq_1_2_disp=false
CSET gtp0_cc_seq_1_2_k=false
CSET gtp0_cc_seq_1_2_mask=true
CSET gtp0_cc_seq_1_3=00000000
CSET gtp0_cc_seq_1_3_disp=false
CSET gtp0_cc_seq_1_3_k=false
CSET gtp0_cc_seq_1_3_mask=true
CSET gtp0_cc_seq_1_4=00000000
CSET gtp0_cc_seq_1_4_disp=false
CSET gtp0_cc_seq_1_4_k=false
CSET gtp0_cc_seq_1_4_mask=true
CSET gtp0_cc_seq_2_1=00000000
CSET gtp0_cc_seq_2_1_disp=false
CSET gtp0_cc_seq_2_1_k=false
CSET gtp0_cc_seq_2_1_mask=true
CSET gtp0_cc_seq_2_2=00000000
CSET gtp0_cc_seq_2_2_disp=false
CSET gtp0_cc_seq_2_2_k=false
CSET gtp0_cc_seq_2_2_mask=true
CSET gtp0_cc_seq_2_3=00000000
CSET gtp0_cc_seq_2_3_disp=false
CSET gtp0_cc_seq_2_3_k=false
CSET gtp0_cc_seq_2_3_mask=true
CSET gtp0_cc_seq_2_4=00000000
CSET gtp0_cc_seq_2_4_disp=false
CSET gtp0_cc_seq_2_4_k=false
CSET gtp0_cc_seq_2_4_mask=true
CSET gtp0_cc_sequence_length=2
CSET gtp0_clk_cor_precedence=CC
CSET gtp0_clk_cor_repeat_wait=0
CSET gtp0_com_burst_val=15
CSET gtp0_comma_alignment=Even_Byte_Boundaries
CSET gtp0_comma_double=false
CSET gtp0_comma_mask=0011111111
CSET gtp0_comma_preset=User_defined
CSET gtp0_dec_mcomma_detect=false
CSET gtp0_dec_pcomma_detect=true
CSET gtp0_dec_valid_comma_only=false
CSET gtp0_decoding=None_(MSB_First)
CSET gtp0_dfe_mode=Fixed_tap_mode
CSET gtp0_disable_ac_coupling=true
CSET gtp0_driver_swing=Use_TXDIFFCTRL_Port
CSET gtp0_en_idle_reset_buf=true
CSET gtp0_enable_dfe=false
CSET gtp0_encoding=None_(MSB_First)
CSET gtp0_errors_to_lose_sync=128
CSET gtp0_fifo_lower_bounds=18
CSET gtp0_fifo_upper_bounds=22
CSET gtp0_highpass_pole_location=Use_RXEQPOLE_Port
CSET gtp0_mcomma_detect=false
CSET gtp0_minus_comma=0000000000
CSET gtp0_pci_express_mode=false
CSET gtp0_pcomma_detect=true
CSET gtp0_pll_sata=false
CSET gtp0_plus_comma=0000110011
CSET gtp0_pma_rx_cfg=0DCE088
CSET gtp0_ppm_offset=0_(Synchronous)
CSET gtp0_prbs_error_threshold=1
CSET gtp0_preemphasis_level=Use_TXPREEMPHASIS_Port
CSET gtp0_protocol_file=Start_from_scratch
CSET gtp0_rx_datapath_width=16
CSET gtp0_rx_decode_seq_match=false
CSET gtp0_rx_divider=/1
CSET gtp0_rx_en_idle_hold_dfe=true
CSET gtp0_rx_idle_hi_cnt=1000
CSET gtp0_rx_idle_lo_cnt=0000
CSET gtp0_rx_line_rate=4.0
CSET gtp0_rx_oob_threshold=111
CSET gtp0_rx_slide_mode=PCS
CSET gtp0_rx_status_fmt=PCIe
CSET gtp0_rx_termination_voltage=VTTRX
CSET gtp0_rxlossofsyncport=false
CSET gtp0_rxrundisp_indicates_cc=false
CSET gtp0_rxusrclk_source=REFCLKOUT
CSET gtp0_sata_burst_val=4
CSET gtp0_sata_idle_val=4
CSET gtp0_second_order_cdr_loop=false
CSET gtp0_termination_imp=50
CSET gtp0_trans_time_from_p2=60
CSET gtp0_trans_time_non_p2=25
CSET gtp0_trans_time_to_p2=100
CSET gtp0_tx_datapath_width=16
CSET gtp0_tx_divider=/1
CSET gtp0_tx_line_rate=4.0
CSET gtp0_txrx_invert=00011
CSET gtp0_txusrclk_source=REFCLKOUT
CSET gtp0_use_cb=false
CSET gtp0_use_cc=false
CSET gtp0_use_comma_detect=true
CSET gtp0_use_ext_cc_module=false
CSET gtp0_use_port_enmcommaalign=false
CSET gtp0_use_port_enpcommaalign=true
CSET gtp0_use_port_loopback=false
CSET gtp0_use_port_phystatus=false
CSET gtp0_use_port_rxbufreset=false
CSET gtp0_use_port_rxbufstatus=false
CSET gtp0_use_port_rxbyteisaligned=true
CSET gtp0_use_port_rxbyterealign=true
CSET gtp0_use_port_rxcdrreset=false
CSET gtp0_use_port_rxchariscomma=false
CSET gtp0_use_port_rxcharisk=false
CSET gtp0_use_port_rxcommadet=true
CSET gtp0_use_port_rxlossofsync=false
CSET gtp0_use_port_rxoversampleerr=false
CSET gtp0_use_port_rxpolarity=false
CSET gtp0_use_port_rxpowerdown=false
CSET gtp0_use_port_rxrecclk=false
CSET gtp0_use_port_rxreset=true
CSET gtp0_use_port_rxrundisp=false
CSET gtp0_use_port_rxslide=false
CSET gtp0_use_port_rxstatus=false
CSET gtp0_use_port_rxvalid=false
CSET gtp0_use_port_txbufstatus=false
CSET gtp0_use_port_txbypass8b10b=false
CSET gtp0_use_port_txchardispmode=false
CSET gtp0_use_port_txchardispval=false
CSET gtp0_use_port_txcomstart=false
CSET gtp0_use_port_txcomtype=false
CSET gtp0_use_port_txdetectrx=false
CSET gtp0_use_port_txelecidle=false
CSET gtp0_use_port_txenprbstst=false
CSET gtp0_use_port_txinhibit=false
CSET gtp0_use_port_txkerr=false
CSET gtp0_use_port_txoutclk=false
CSET gtp0_use_port_txpolarity=false
CSET gtp0_use_port_txpowerdown=false
CSET gtp0_use_port_txreset=false
CSET gtp0_use_port_txrundisp=false
CSET gtp0_use_prbs_detector=false
CSET gtp0_use_resistor_cal_circuit=false
CSET gtp0_use_rx_eq=false
CSET gtp0_use_rx_oob=false
CSET gtp0_use_rxbuffer=true
CSET gtp0_use_turbo_mode=false
CSET gtp0_use_two_cb_sequences=false
CSET gtp0_use_two_cc_sequences=false
CSET gtp0_wideband_highpass_mix=Use_RXEQMIX_Port
CSET gtp1_bytes_to_reduce_error=8
CSET gtp1_cb_seq_1_1=00000000
CSET gtp1_cb_seq_1_1_disp=false
CSET gtp1_cb_seq_1_1_k=false
CSET gtp1_cb_seq_1_1_mask=true
CSET gtp1_cb_seq_1_2=00000000
CSET gtp1_cb_seq_1_2_disp=false
CSET gtp1_cb_seq_1_2_k=false
CSET gtp1_cb_seq_1_2_mask=true
CSET gtp1_cb_seq_1_3=00000000
CSET gtp1_cb_seq_1_3_disp=false
CSET gtp1_cb_seq_1_3_k=false
CSET gtp1_cb_seq_1_3_mask=true
CSET gtp1_cb_seq_1_4=00000000
CSET gtp1_cb_seq_1_4_disp=false
CSET gtp1_cb_seq_1_4_k=false
CSET gtp1_cb_seq_1_4_mask=true
CSET gtp1_cb_seq_2_1=00000000
CSET gtp1_cb_seq_2_1_disp=false
CSET gtp1_cb_seq_2_1_k=false
CSET gtp1_cb_seq_2_1_mask=true
CSET gtp1_cb_seq_2_2=00000000
CSET gtp1_cb_seq_2_2_disp=false
CSET gtp1_cb_seq_2_2_k=false
CSET gtp1_cb_seq_2_2_mask=true
CSET gtp1_cb_seq_2_3=00000000
CSET gtp1_cb_seq_2_3_disp=false
CSET gtp1_cb_seq_2_3_k=false
CSET gtp1_cb_seq_2_3_mask=true
CSET gtp1_cb_seq_2_4=00000000
CSET gtp1_cb_seq_2_4_disp=false
CSET gtp1_cb_seq_2_4_k=false
CSET gtp1_cb_seq_2_4_mask=true
CSET gtp1_cb_sequence_1_max_skew=1
CSET gtp1_cb_sequence_2_max_skew=1
CSET gtp1_cb_sequence_length=1
CSET gtp1_cc_keep_one_idle=false
CSET gtp1_cc_seq_1_1=00000000
CSET gtp1_cc_seq_1_1_disp=false
CSET gtp1_cc_seq_1_1_k=false
CSET gtp1_cc_seq_1_1_mask=true
CSET gtp1_cc_seq_1_2=00000000
CSET gtp1_cc_seq_1_2_disp=false
CSET gtp1_cc_seq_1_2_k=false
CSET gtp1_cc_seq_1_2_mask=true
CSET gtp1_cc_seq_1_3=00000000
CSET gtp1_cc_seq_1_3_disp=false
CSET gtp1_cc_seq_1_3_k=false
CSET gtp1_cc_seq_1_3_mask=true
CSET gtp1_cc_seq_1_4=00000000
CSET gtp1_cc_seq_1_4_disp=false
CSET gtp1_cc_seq_1_4_k=false
CSET gtp1_cc_seq_1_4_mask=true
CSET gtp1_cc_seq_2_1=00000000
CSET gtp1_cc_seq_2_1_disp=false
CSET gtp1_cc_seq_2_1_k=false
CSET gtp1_cc_seq_2_1_mask=true
CSET gtp1_cc_seq_2_2=00000000
CSET gtp1_cc_seq_2_2_disp=false
CSET gtp1_cc_seq_2_2_k=false
CSET gtp1_cc_seq_2_2_mask=true
CSET gtp1_cc_seq_2_3=00000000
CSET gtp1_cc_seq_2_3_disp=false
CSET gtp1_cc_seq_2_3_k=false
CSET gtp1_cc_seq_2_3_mask=true
CSET gtp1_cc_seq_2_4=00000000
CSET gtp1_cc_seq_2_4_disp=false
CSET gtp1_cc_seq_2_4_k=false
CSET gtp1_cc_seq_2_4_mask=true
CSET gtp1_cc_sequence_length=2
CSET gtp1_clk_cor_precedence=CC
CSET gtp1_clk_cor_repeat_wait=0
CSET gtp1_com_burst_val=15
CSET gtp1_comma_alignment=Even_Byte_Boundaries
CSET gtp1_comma_double=false
CSET gtp1_comma_mask=0011111111
CSET gtp1_comma_preset=User_defined
CSET gtp1_dec_mcomma_detect=false
CSET gtp1_dec_pcomma_detect=true
CSET gtp1_dec_valid_comma_only=false
CSET gtp1_decoding=None_(MSB_First)
CSET gtp1_dfe_mode=Fixed_tap_mode
CSET gtp1_disable_ac_coupling=true
CSET gtp1_driver_swing=Use_TXDIFFCTRL_Port
CSET gtp1_en_idle_reset_buf=true
CSET gtp1_enable_dfe=false
CSET gtp1_encoding=None_(MSB_First)
CSET gtp1_errors_to_lose_sync=128
CSET gtp1_fifo_lower_bounds=18
CSET gtp1_fifo_upper_bounds=22
CSET gtp1_highpass_pole_location=Use_RXEQPOLE_Port
CSET gtp1_mcomma_detect=false
CSET gtp1_minus_comma=0000000000
CSET gtp1_pci_express_mode=false
CSET gtp1_pcomma_detect=true
CSET gtp1_pll_sata=false
CSET gtp1_plus_comma=0000110011
CSET gtp1_pma_rx_cfg=0DCE088
CSET gtp1_ppm_offset=0_(Synchronous)
CSET gtp1_prbs_error_threshold=1
CSET gtp1_preemphasis_level=Use_TXPREEMPHASIS_Port
CSET gtp1_protocol_file=Use_GTX0_settings
CSET gtp1_rx_datapath_width=16
CSET gtp1_rx_decode_seq_match=false
CSET gtp1_rx_divider=/1
CSET gtp1_rx_en_idle_hold_dfe=true
CSET gtp1_rx_idle_hi_cnt=1000
CSET gtp1_rx_idle_lo_cnt=0000
CSET gtp1_rx_line_rate=4.0
CSET gtp1_rx_oob_threshold=111
CSET gtp1_rx_slide_mode=PCS
CSET gtp1_rx_status_fmt=PCIe
CSET gtp1_rx_termination_voltage=VTTRX
CSET gtp1_rxlossofsyncport=false
CSET gtp1_rxrundisp_indicates_cc=false
CSET gtp1_rxusrclk_source=REFCLKOUT
CSET gtp1_sata_burst_val=4
CSET gtp1_sata_idle_val=4
CSET gtp1_second_order_cdr_loop=false
CSET gtp1_termination_imp=50
CSET gtp1_trans_time_from_p2=60
CSET gtp1_trans_time_non_p2=25
CSET gtp1_trans_time_to_p2=100
CSET gtp1_tx_datapath_width=16
CSET gtp1_tx_divider=/1
CSET gtp1_tx_line_rate=4.0
CSET gtp1_txrx_invert=00011
CSET gtp1_txusrclk_source=REFCLKOUT
CSET gtp1_use_cb=false
CSET gtp1_use_cc=false
CSET gtp1_use_comma_detect=true
CSET gtp1_use_ext_cc_module=false
CSET gtp1_use_port_enmcommaalign=false
CSET gtp1_use_port_enpcommaalign=true
CSET gtp1_use_port_loopback=false
CSET gtp1_use_port_phystatus=false
CSET gtp1_use_port_rxbufreset=false
CSET gtp1_use_port_rxbufstatus=false
CSET gtp1_use_port_rxbyteisaligned=true
CSET gtp1_use_port_rxbyterealign=true
CSET gtp1_use_port_rxcdrreset=false
CSET gtp1_use_port_rxchariscomma=false
CSET gtp1_use_port_rxcharisk=false
CSET gtp1_use_port_rxcommadet=true
CSET gtp1_use_port_rxlossofsync=false
CSET gtp1_use_port_rxoversampleerr=false
CSET gtp1_use_port_rxpolarity=false
CSET gtp1_use_port_rxpowerdown=false
CSET gtp1_use_port_rxrecclk=false
CSET gtp1_use_port_rxreset=true
CSET gtp1_use_port_rxrundisp=false
CSET gtp1_use_port_rxslide=false
CSET gtp1_use_port_rxstatus=false
CSET gtp1_use_port_rxvalid=false
CSET gtp1_use_port_txbufstatus=false
CSET gtp1_use_port_txbypass8b10b=false
CSET gtp1_use_port_txchardispmode=false
CSET gtp1_use_port_txchardispval=false
CSET gtp1_use_port_txcomstart=false
CSET gtp1_use_port_txcomtype=false
CSET gtp1_use_port_txdetectrx=false
CSET gtp1_use_port_txelecidle=false
CSET gtp1_use_port_txenprbstst=false
CSET gtp1_use_port_txinhibit=false
CSET gtp1_use_port_txkerr=false
CSET gtp1_use_port_txoutclk=false
CSET gtp1_use_port_txpolarity=false
CSET gtp1_use_port_txpowerdown=false
CSET gtp1_use_port_txreset=false
CSET gtp1_use_port_txrundisp=false
CSET gtp1_use_prbs_detector=false
CSET gtp1_use_resistor_cal_circuit=false
CSET gtp1_use_rx_eq=false
CSET gtp1_use_rx_oob=false
CSET gtp1_use_rxbuffer=true
CSET gtp1_use_turbo_mode=false
CSET gtp1_use_two_cb_sequences=false
CSET gtp1_use_two_cc_sequences=false
CSET gtp1_use_txbuffer=true
CSET gtp1_wideband_highpass_mix=Use_RXEQMIX_Port
CSET gtx_column=right
CSET int_data_width=16
CSET oob_clk_divider=0000000
CSET pll_clock=4
CSET pll_rate=2.0
CSET pref_int_width=20
CSET refclk_ac_coupling_x0_y0=false
CSET refclk_ac_coupling_x0_y1=false
CSET refclk_ac_coupling_x0_y10=false
CSET refclk_ac_coupling_x0_y11=false
CSET refclk_ac_coupling_x0_y2=false
CSET refclk_ac_coupling_x0_y3=false
CSET refclk_ac_coupling_x0_y4=false
CSET refclk_ac_coupling_x0_y5=false
CSET refclk_ac_coupling_x0_y6=false
CSET refclk_ac_coupling_x0_y7=false
CSET refclk_ac_coupling_x0_y8=false
CSET refclk_ac_coupling_x0_y9=false
CSET refclk_x0_y0=------
CSET refclk_x0_y1=------
CSET refclk_x0_y10=------
CSET refclk_x0_y11=------
CSET refclk_x0_y2=CLK_Y2
CSET refclk_x0_y3=CLK_Y3
CSET refclk_x0_y4=CLK_Y5
CSET refclk_x0_y5=CLK_Y5
CSET refclk_x0_y6=------
CSET refclk_x0_y7=------
CSET refclk_x0_y8=------
CSET refclk_x0_y9=------
CSET reference_clock=250.00
CSET rx_en_idle_hold_cdr=false
CSET rx_en_idle_reset_fr=true
CSET rx_en_idle_reset_ph=true
CSET silicon_version=PRODUCTION
CSET termination_ctrl=10100
CSET termination_ovrd=false
CSET use_gtp_dual_x0_y0=false
CSET use_gtp_dual_x0_y1=false
CSET use_gtp_dual_x0_y10=false
CSET use_gtp_dual_x0_y11=false
CSET use_gtp_dual_x0_y2=false
CSET use_gtp_dual_x0_y3=false
CSET use_gtp_dual_x0_y4=true
CSET use_gtp_dual_x0_y5=true
CSET use_gtp_dual_x0_y6=false
CSET use_gtp_dual_x0_y7=false
CSET use_gtp_dual_x0_y8=false
CSET use_gtp_dual_x0_y9=false
CSET use_port_drp=false
CSET use_port_plllkdet=true
CSET use_port_plllkdeten=true
CSET use_port_pllpowerdown=false
CSET use_port_refclkout=true
CSET use_port_refclkpowerdown=false
CSET use_txbuffer=true
# END Parameters
GENERATE
# CRC: b5c04a6a
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