此verilog文件：
module SPI_module # (
parameter TBUS_WIDTH = 24,
parameter SPI_CLK_DIVIDE = 16,
parameter REG_WORD_SIZE = 24,
parameter REG_ADDR_WIDTH = 8
)(
input clk,
input rst,
output reg sdo,
output reg cs,
output reg sclk,
input [REG_WORD_SIZE+REG_ADDR_WIDTH-1:0] tdata,
input [31:0] spi_start,
output [31:0] spi_busy
);
assign start = spi_start[0];
assign spi_busy[0] = ~busy;
localparam IDLE = 1'b0;
localparam TRANS = 1'b1;
localparam CNT = 1'b1;
reg [REG_WORD_SIZE+REG_ADDR_WIDTH-1:0] tdata_reg;
reg [4:0] bit_cnt = 0;
reg start_reg1=0, start_reg2=0;
reg tstart = 0;
reg state = IDLE;
reg tx_start = 0;
reg [4:0] bit_cnt_reg;
reg cnt_state = 0;
assign busy = cs;
always @ (posedge clk)
bit_cnt_reg <= bit_cnt;
always @ (posedge clk)
if (rst == 1'b1) begin
start_reg1 <= 0;
start_reg2 <= 0;
tstart <= 0;
end else begin
start_reg1 <= start;
start_reg2 <= start_reg1;
if (start_reg1 == 1'b1 && start_reg2 == 1'b0) begin
tstart <= 1'b1;
end else begin
tstart <= 1'b0;
end
end
reg [5:0] cnt = 0;
always @ (posedge clk)
if (rst==1) begin
cnt <= 0;
cnt_state <= IDLE;
end else begin
case(cnt_state)
IDLE: begin
if (tstart==1) begin cnt<=1; cnt_state <= CNT; tdata_reg <= tdata; end else begin cnt<=0; cnt_state <= IDLE; end
end
CNT: begin
if (bit_cnt_reg == REG_WORD_SIZE+REG_ADDR_WIDTH-1 && bit_cnt ==0 ) begin
cnt <= 0; cnt_state <= IDLE;
end else if ( cnt==SPI_CLK_DIVIDE-1 ) cnt <= 1;
else cnt <= cnt+1;
end
endcase
end
always @ (posedge clk)
if (rst==1) begin
cs <= 0;
sdo <= 1'bx;
sclk <= 1'b0;
bit_cnt <= 0;
end else begin
case (cnt)
0: begin
cs <= 0;
sclk <= 0;
sdo <= 1'bx;
bit_cnt <= 0;
end
1: begin
cs <=1;
sclk <= 0;
sdo <= tdata_reg[REG_WORD_SIZE+REG_ADDR_WIDTH-bit_cnt-1];
end
SPI_CLK_DIVIDE/2 : begin
cs<=1; sclk <= 1;
sdo <= tdata_reg[REG_WORD_SIZE+REG_ADDR_WIDTH-bit_cnt-1];
end
SPI_CLK_DIVIDE-1: begin
if (bit_cnt==REG_WORD_SIZE+REG_ADDR_WIDTH-1) bit_cnt <= 0;
else bit_cnt <= bit_cnt +1;
end
default: begin cs <= cs; sdo <= sdo; sclk<= sclk; end
endcase
end
endmodule
在此verilog文件中，没发现start的定义，是不是就说明start是1位的wire？wire是不是相关于VHDL中的signal？
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