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The Hynix HY57V641620E(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth.<br />HY57V641620E(L/S)T(P) is organized as 4banks of1,048,576x16. HY57V641620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock.<br />All inputsand outputs are synchronized with the rising edge of the clock input.<br />The data paths are internally pipelined to achieve very high bandwidth.<br />All input and output voltage levels are compatible with LVTTL.<br /><br />Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave).<br />A burst of read or write cycles in progress can be terminated by a burst terminate command orcan be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)<br /> |
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