本帖最后由 sunt8707 于 2010-10-26 14:37 编辑
该状态机用case语句实现的代码为：
module fsm_onehot(rst_n,w,clk,z);
input rst_n,w,clk;
output reg z;
reg [8:0]state,next_state;
parameter A=9'b000000001,
B=9'b000000010,
C=9'b000000100,
D=9'b000001000,
E=9'b000010000,
F=9'b000100000,
G=9'b001000000,
H=9'b010000000,
I=9'b100000000;
always @(posedge clk)
begin
if(!rst_n)
state<=A;
else
state<=next_state;
end
[email=always@ (state]always @ (state[/email] or A or B or C or D or E or F or G or H or I)
begin
case (state)
A: begin
if(w)
next_state <= F;
else
next_state <= B;
end
B: begin
if(w)
next_state <= F;
else
next_state <= C;
end
C: begin
if(w)
next_state <= F;
else
next_state <= D;
end
D: begin
if(w)
next_state <= F;
else
next_state <= E;
end
E: begin
if(w)
next_state <= F;
else
next_state <= E;
end
F: begin
if(w)
next_state <= G;
else
next_state <= B;
end
G: begin
if(w)
next_state <= H;
else
next_state <= B;
end
H: begin
if(w)
next_state <= I;
else
next_state <= B;
end
I: begin
if(w)
next_state <= I;
else
next_state <= B;
end
default: next_state<=A;
endcase
end
[email=always@(state]always@(state[/email])
begin
case (state)
A: z=1'b0;
B: z=1'b0;
C: z=1'b0;
D: z=1'b0;
E: z=1'b1;
F: z=1'b0;
G: z=1'b0;
H: z=1'b0;
I: z=1'b1;
default: z=1'b0;
endcase
end
endmodule
请问各位大哥，如何用assign语句实现这个状态机？具体是调用9个触发器来实现这个FSM,用assign语句连接触发器的输入。哪位高手知道，请指点一下，小弟初学，不胜感激！！！ |
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