library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt is
port( clk : in std_logic;
--cnt_out: out std_logic_vector(7 downto 0);
q : out std_logic);
end entity;
architecture bhv of cnt is
signal cnt : std_logic_vector(7 downto 0); --255
signal q1 : std_logic;
begin
process(clk)
begin
if clk'event and clk='1'then
cnt <= cnt + '1';
if cnt=5 then --(cnt=? any divid num you want but <255)
q1 <= not(q1);
cnt<="00000000";
else q1 <= q1;
end if;
cnt_out<=cnt;
q<=q1;
end if;
end process;
end;
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