2.发送数据模块
module
my_uart_tx(clk, rst_n, tx, key_input);
input
clk,rst_n;
input
key_input;
//按键输入
output
tx;
//串行数据发送端
assign
tx = txd_reg;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)begin
cnt_delay <= 0;
start_delaycnt <= 0;
end
else if(start_delaycnt) begin
if(cnt_delay != 23'd8000000) begin
cnt_delay <= cnt_delay + 1;
end
else begin
cnt_delay <= 0;
start_delaycnt <= 0;
end
end
else
begin
if(!key_input && cnt_delay == 0)
start_delaycnt <= 1;
end
end
//**********************************************************//
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
key_entry1 <= 0;
else
begin
if(key_entry2)
key_entry1 <= 0;
else if(cnt_delay == 23'd8000000) begin
if(!key_input)
key_entry1 <= 1;
end
end
end
//**********************************************************//
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
div_reg <= 0;
else
begin
if(div_reg == div_par - 1)
div_reg <= 0;
else
div_reg <= div_reg + 1;
end
end
always@(posedge clk or negedge rst_n)
//分频得到8倍波特率的时钟
begin
if(!rst_n)
clkbaud8x <= 0;
else if(div_reg == div_par - 1)
clkbaud8x <= ~clkbaud8x;
end
always@(posedge clkbaud8x or negedge rst_n)
begin
if(!rst_n)
div8_tras_reg <= 0;
else if(trasstart)
div8_tras_reg <= div8_tras_reg + 1;
//发送开始后，时隙数在8倍波特率的时钟下加1循环
end
//**********************************************************//
always@(div8_tras_reg)
begin
if(div8_tras_reg == 7)
clkbaud_tras = 1;
//在第7个时隙，发送使能信号有效，将数据发出
else
clkbaud_tras = 0;
end
//**********************************************************//
always@(posedge clkbaud8x or negedge rst_n)
begin
if(!rst_n) begin
txd_reg <= 1;
trasstart <= 0;
txd_buf <= 0;
state_tras <= 0;
send_state <= 0;
key_entry2 <= 0;
end
else begin
if(!key_entry2) begin
if(key_entry1) begin
key_entry2 <= 1;
txd_buf <= 8'h43;
end
end
else begin
case(state_tras)
4'b0000:
begin
//发送起始位
if(!trasstart && send_state < 3)
trasstart <= 1;
else if(send_state < 3)
begin
if(clkbaud_tras)
begin
txd_reg <= 0;
state_tras <= state_tras + 1;end end
else
begin
key_entry2 <= 0;
send_state <= 0;
state_tras <= 0;
end end
4'b0001:
begin //发送第1位
if(clkbaud_tras)
begin
txd_reg <= txd_buf[0];
txd_buf[6:0] <= txd_buf[7:1];
state_tras <= state_tras + 1;
end end
4'b0010:
begin //发送第2位
if(clkbaud_tras)
begin
txd_reg <= txd_buf[0];
txd_buf[6:0] <= txd_buf[7:1];
state_tras <= state_tras + 1;
end end
4'b0011:
begin //发送第3位
if(clkbaud_tras)
begin
txd_reg <= txd_buf[0];
txd_buf[6:0] <= txd_buf[7:1];
state_tras <= state_tras + 1;
end end
4'b0100:
begin //发送第4位
if(clkbaud_tras)
begin
txd_reg <= txd_buf[0];
txd_buf[6:0] <= txd_buf[7:1];
state_tras <= state_tras + 1;
end end
4'b0101:
begin //发送第5位
if(clkbaud_tras)
begin
txd_reg <= txd_buf[0];
txd_buf[6:0] <= txd_buf[7:1];
state_tras <= state_tras + 1;
end end
4'b0110:
begin //发送第6位
if(clkbaud_tras)
begin
txd_reg <= txd_buf[0];
txd_buf[6:0] <= txd_buf[7:1];
state_tras <= state_tras + 1;
end end
4'b0111:
begin //发送第7位
if(clkbaud_tras)
begin
txd_reg <= txd_buf[0];
txd_buf[6:0] <= txd_buf[7:1];
state_tras <= state_tras + 1;
end end
4'b1000:
begin //发送第8位
if(clkbaud_tras)
begin
txd_reg<=txd_buf[0];
txd_buf[6:0]<=txd_buf[7:1];
state_tras<=state_tras+1;
end
end
4'b1001: begin //发送停止位
if(clkbaud_tras) begin
txd_reg<=1;
txd_buf<=8'h55;
state_tras<=state_tras+1;
end
end
4'b1111:begin
if(clkbaud_tras) begin
state_tras<=state_tras+1;
send_state<=send_state+1;
trasstart<=0;
case(send_state)
3'b00:
txd_buf<=8'h03;
3'b01:
txd_buf<=8'h01;
default:
txd_buf<=0;
endcase
end
end
default: begin
if(clkbaud_tras) begin
state_tras<=state_tras+1;
trasstart<=1;
end
end
endcase
end
end
end
endmodule
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