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Cortex M3 BRCHSTAT usage

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冰糖炖雪梨|  楼主 | 2018-9-8 21:16 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
I am looking for a way to enhance CM3 performance especially branch. Following is what I found in TRM that BRCHSTAT seems to give user information of current pipeline status and it can be used to enhance CM3 performance.
I am wondering how to do it?
I read this and think BRCHSTAT should be for low speed memory application since controller usually implement prefetch buffer (similar to cache) and BRCHSTAT can be used to prefetch. I understand branch forwarding is beneficial, but how do we use BRCHSTAT? I also do a research that BRCHSTAT are connected to ETM in integration and that is the only information about the usage.
//
The following scenarios show how you can use branch forwarding and the BRCHSTAT control to get the best performance from your memory system. The scenarios focus on the ideal Harvard setup, where instructions execute from ICODE, literals execute from DCODE (unified to ICODE), and stack/heap/application data executes from SYSTEM.
Zero waitstate
Zero waitstate, registered fetch interface (ICODE)
One wait state flash
One wait state flash, registered fetch interface (ICODE)
Two wait states flash.
//*
Another question is what is the \"branch backward\" mean. I understand branch forwarding, but what is the idea of backwarding?

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