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类型为wire或类似数据类型的wire的信号需要连续分配值。 例如，考虑用于连接电路板上的部件的电线。 只要将+ 5V电池应用于导线的一端，连接到导线另一端的组件将获得所需的电压。
在Verilog中，这个概念是通过一个赋值语句实现的，其中任何连接或其他类似的连接(比如数据类型)都可以使用一个值连续驱动。该值可以是常量，也可以是由一组信号组成的表达式。 赋值语法以关键字Assign开头，后跟信号名，可以是单个信号，也可以是不同信号网络的串联。驱动强度和延迟是可选的，主要用于数据流建模，而不是集成到实际硬件中。对右侧的表达式或信号求值并赋值给左侧的nets的表达式。 assign <net_expression> = [drive_strength] [delay] <expression of different signals or constant value>
延迟值对于为gates指定延迟非常有用，并且用于在真实的硬件中建模定时行为，因为该值指示了何时应该用所评估的值分配网络(net)。 规则使用assign语句时，需要遵循一些规则：
【1】LHS应该始终是标量或向量网络，或者标量或向量网络的串联，而绝对不能是标量或向量寄存器；
【2】RHS可以包含标量或向量寄存器和函数调用；
【3】只要RHS上的任何操作数的值发生变化，LHS就会使用新值进行更新；
【4】Assign语句也称为连续分配，并且始终处于活动状态。
在下面的例子中，一个叫out的网络是由一个信号表达式连续驱动的,i1和i2用逻辑&构成表达式。
如果将wire转换为端口并进行合成，我们将在合成后得到如下所示的RTL示意图。
 module xyz (input [3:0] x, // x is a 4-bit vector net
input y, // y is a scalar net (1-bit)
output [4:0] z ); // z is a 5-bit vector net
wire [1:0] a;
wire b;
// Assume one of the following assignments are chosen in real design
// If x='hC and y='h1 let us see the value of z
// Case #1: 4-bits of x and 1 bit of y is concatenated to get a 5-bit net
// and is assigned to the 5-bit nets of z. So value of z='b11001 or z='h19
assign z = {x, y};
// Case #2: 4-bits of x and 1 bit of y is concatenated to get a 5-bit net
// and is assigned to selected 3-bits of net z. Remaining 2 bits of z remains
// undriven and will be high-imp. So value of z='bZ001Z
assign z[3:1] = {x, y};
// Case #3: The same statement is used but now bit4 of z is driven with a constant
// value of 1. Now z = 'b1001Z because only bit0 remains undriven
assign z[3:1] = {x, y};
assign z[4] = 1;
// Case #4: Assume bit3 is driven instead, but now there are two drivers for bit3,
// and both are driving the same value of 0. So there should be no contention and
// value of z = 'bZ001Z
assign z[3:1] = {x, y};
assign z[3] = 0;
// Case #5: Assume bit3 is instead driven with value 1, so now there are two drivers
// with different values, where the first line is driven with the value of X which
// at the time is 0 and the second assignment where it is driven with value 1, so
// now it becomes unknown which will win. So z='bZX01Z
assign z[3:1] = {x, y};
assign z[3] = 1;
// Case #6: Partial selection of operands on RHS is also possible and say only 2-bits
// are chosen from x, then z = 'b00001 because z[4:3] will be driven with 0
assign z = {x[1:0], y};
// Case #7: Say we explicitly assign only 3-bits of z and leave remaining unconnected
// then z = 'bZZ001
assign z[2:0] = {x[1:0], y};
// Case #8: Same variable can be used multiple times as well and z = 'b00111
// 3{y} is the same as {y, y, y}
assign z = {3{y}};
// Case #9: LHS can also be concatenated: a is 2-bit vector and b is scalar
// RHS is evaluated to 11001 and LHS is 3-bit wide so first 3 bits from LSB of RHS
// will be assigned to LHS. So a = 'b00 and b ='b1
assign {a, b} = {x, y};
// Case #10: If we reverse order on LHS keeping RHS same, we get a = 'b01 and b='b0
assign {a, b} = {x, y};
endmodule
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