本帖最后由 sahh 于 2012-8-21 09:48 编辑
代码用modelsim仿真，vlog已经过了，但是vsim报错。
** Fatal: (vsim-3695) ../src/ram_256x40/block_ram_256x40_wrap.sv(0): The interface port 'port_a' must be passed an actual interface.
代码如下：
interface block_ram_IF;
logic [7:0] block_addr_wr;
logic block_wren;
logic [39:0] block_data_wr;
wire clk_block_wr;
logic [7:0] block_addr_rd;
logic [39:0] block_data_rd;
wire clk_block_rd;
modport to_block_ram (
output clk_block_wr,
output clk_block_rd,
output block_wren,
output block_addr_wr,
output block_data_wr,
output block_addr_rd,
input block_data_rd
);
modport block_ram (
input clk_block_wr,
input clk_block_rd,
input block_wren,
input block_addr_wr,
input block_data_wr,
input block_addr_rd,
output block_data_rd
);
endinterface
module block_ram_256x40_wrap (
input mode,
input a_b,
block_ram_IF.block_ram port_a,
block_ram_IF.block_ram port_b,
block_ram_IF.block_ram port_c
);
wire [7:0] wraddress;
wire wrclock;
wire wren;
wire [39:0] data;
wire rdaddress;
wire rdclock;
wire [39:0] q;
assign wraddress = (a_b) ? port_a.block_addr_wr : port_b.block_addr_wr;
assign wrclock = (a_b) ? port_a.clk_block_wr : port_b.clk_block_wr;
assign wren = (mode) ? ((plot_a_b) ? port_a.block_wren : port_b.block_wren) : 1'b0;
assign data = (a_b) ? port_a.block_data_wr : port_b.block_data_wr;
assign rdaddress = (mode) ? ((a_b) ? port_a.block_addr_rd : port_b.block_addr_rd) : port_c.block_addr_rd;
assign rdclock = (mode) ? ((a_b) ? port_a.clk_block_rd : port_b.clk_block_rd) : port_c.clk_block_rd;
assign port_a.block_data_rd = q;
assign port_b.block_data_rd = q;
assign port_c.block_data_rd = q;
ram_256x40 u_block_ram (
// write
.wraddress ( wraddress ), // input [7:0]
.wrclock ( wrclock ), // input
.wren ( wren ), // input
.data ( data ), // input [39:0]
// read
.rdaddress ( rdaddress ), // input [7:0]
.rdclock ( rdclock ), // input
.q ( q ) // output [39:0]
);
endmodule |
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