module easy(f8,f7,f6,f5,f4,f3,f2,f1,O6,O7,O8,pl,cp,ds);
input f8,f7,f6,f5,f4,f3,f2,f1;
input pl,cp,ds；
output O6,O7,O8;
reg [7:0] fifo;
reg [7:0] buff;
reg state1;
///////////////////////
assign O6= pl? f6: ( state1?buff[5]:(fifo[5]) );
assign O7= pl? f7: ( state1?buff[6]:(fifo[6]) );
assign O8= pl? f8: ( state1?buff[7]:(fifo[7]) );
/////////////////////////
always@(posedge pl or posedge cp)
if(pl)
state1<=1;
else
state1<=0;
//////////////////////////
always @(negedge pl)
buff<={f8,f7,f6,f5,f4,f3,f2,f1};
/////////////////////////
always@(posedge cp)
if(state1)
fifo<={buff[6:0],ds};
else
fifo<={fifo[6:0],ds};
////////////////////////
endmodule |
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