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module easy(f8,f7,f6,f5,f4,f3,f2,f1,O6,O7,O8,pl,cp,ds); <br />input f8,f7,f6,f5,f4,f3,f2,f1;<br />input pl,cp,ds；<br />output O6,O7,O8; <br />reg [7:0] fifo;<br />reg [7:0] buff;<br />reg state1;<br />///////////////////////<br />assign O6= pl? f6: ( state1?buff[5]:(fifo[5]) );<br />assign O7= pl? f7: ( state1?buff[6]:(fifo[6]) );<br />assign O8= pl? f8: ( state1?buff[7]:(fifo[7]) ); <br />/////////////////////////<br />always@(posedge pl or posedge cp)<br />if(pl)<br /> state1<=1;<br />else<br /> state1<=0;<br />//////////////////////////<br />always @(negedge pl)<br />buff<={f8,f7,f6,f5,f4,f3,f2,f1};<br />/////////////////////////<br />always@(posedge cp)<br />if(state1)<br /> fifo<={buff[6:0],ds};<br />else <br /> fifo<={fifo[6:0],ds}; <br />////////////////////////<br /> <br />endmodule
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