module cy4(input S,
input R,
input clk,
input rst_n,
output reg Q
);
always @(posedge clk or negedge rst_n)
if(!rst_n) Q <= 1'b0;
else
case({S,R})
2'b00: Q <= Q;
2'b01: Q <= 1'b0;
2'b10: Q <= 1'b1;
2'b11: Q <= 1'bx;
endcase
endmodule![]()
测试脚本代码：
`timescale 1 ns/ 1 ps
module cy4_vlg_tst();
reg R;
reg S;
reg clk;
reg rst_n;
wire Q; cy4 i1 (
.Q(Q),
.R(R),
.S(S),
.clk(clk),
.rst_n(rst_n)
);
initial
begin
clk = 0;
rst_n = 0; 10;rst_n = 1;
S = 0;
R = 0; 50;S = 0;
R = 1; 50;S = 1;
R = 0; 50;S = 1;
R = 1; 50;<span id="MathJax-Element-1-Frame" tabindex="0" data-mathml="stop;" role="presentation" style="box-sizing: border-box; border: 0px; font: inherit; vertical-align: baseline; position: relative;">stop;stop;display(“Running testbench”);
end
always #10 clk = ~clk;
endmodule
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