例说Verilog和VHDL的区别，助你选择适合自己的硬件描述语言

type int_8bit is range 0 to 255 -- define 8-bit unsigned numbers

signal i : int_8bit;

type state_FSM is (Idle, start, calculate , finish, delay) 

-- define symbolic states to represent FSM states.

signal current_state, next_state: state_FSM;

package fsm_type is 

type FSM_states is (IDLE, TRANSMIT, RECEIVE, STOP);

end package

-- to use the FSM_states type in an entity or architecture

-- use the following statement on top of the entity

use work.fsm_type.all

entity example is

// Below is the content of "VerilogVsVHDL.h" file

`define INPUT_VERILOG "./test_VerilogvsVHDL.hex" // Input file name 

`define OUTPUT_VHDL "VHDL.bmp" // Output file name 

`define VERILOG_VHDL_DIFFERENCE



// Then call it in every single module that you want to use the definition above

`include "VerilogVsVHDL.h"

entity BUF is

 generic (DELAY : TIME := 10 ns);

 port ( BUF_IN : in BIT; BUF_OUT : out BIT);

end BUF;

-- The first design architecture for BUF 

architecture STRUCT_BUF1 of BUF is

signal temp: bit;

begin

  BUF_OUT <= not temp after DELAY;

  temp <= not BUF_IN after DELAY;

end STRUCT_BUF1;

-- The second design architecture for BUF 

architecture STRUCT_BUF2 of BUF is

begin

  BUF_OUT <= BUF_IN after 2*DELAY;;

end STRUCT_BUF2;

-- Testbench to simulate BUF entity 

entity BUF_TESTBENCH is 

end BUF_TESTBENCH;

architecture STRUCT_BUF_TEST of BUF_TESTBENCH is

signal TEST1, TEST2 : BIT := '1';

-- BUF_COMP component declaration:

component BUF_COMP is

 generic (TIME_DELAY : TIME);

 port ( IN1 : in BIT; OUT1 : out BIT );

end component;

begin

  -- instantiation of BUF_COMP component:

  DUT:BUF_COMP generic map (10 ns) port map (TEST1,TEST2);

end STRUCT_BUF_TEST;

-- Configuration specify the design entity and architecture

-- for the DUT component instance in the testbench above

configuration CONFIG_BUF of TEST_BUF is

-- Associate BUF_COMP component instance to BUF design entity

-- and STRUCT_BUF1 design architecture for simulation 

for STRUCT_BUF_TEST 

 for DUT : BUF_COMP 

 use entity WORK.BUF (STRUCT_BUF1)

 generic map (DELAY => TIME_DELAY)

 port map (BUF_IN => IN1, BUF_OUT => OUT1);

 end for;

end for ;

end CONFIG_BUF;

-- library management in VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.numeric_std.all;

use work.clock_div.all;

signal test_reg1:  std_logic_vector(3 downto 0); 

signal test_reg2:  std_logic_vector(7 downto 0); 

test_reg2 <= test_reg1;

-- You cannot assign a 4-bit signal to an 8-bit signal 

-- in VHDL, it will introduce a syntax error below:

-- Width mismatch. Expected width 8, Actual width is 4 

-- for dimension 1 of test_reg1.

 wire [3:0] test1;

 wire [7:0] test2;

  // In Verilog, you can assign 4-bit signal to 8-bit signal.

 assign test2 = test1;

  // there will be no syntax error during synthesis 

signal test1: std_logic_vector(7 downto 0);

signal test2: integer;

test2 <= test1;

-- Syntax Error: type of test2 is incompatile with type of test1 

library IEEE;

USE ieee.numeric_std.ALL;

signal test1: std_logic_vector(3 downto 0);

signal test2: integer;

-- Use IEEE.NUMBERIC_STD.ALL Library for this conversion

test2 <= to_integer(unsigned(test1));

-- No syntax errors this time

reg [3:0] test1;

 integer test2;

 always @(test1) begin

   test2 = test1;

 end

         // NO syntax errors when compiling

-- VHDL code for ALU 

process(SEL,ABUS,BBUS,tmp1,tmp2)

begin 

case(SEL) is

 when "0000" =>  ALUOUT <= tmp1; -- ADD

 when "0001" =>  ALUOUT <= tmp2;-- SUB 

 when "0010" =>  ALUOUT <= BBUS; -- AND

 when others => ALUOUT <= ABUS; 

 end case;

end process;

// Verilog equivalent to VHDL ALU 

assign ALUOUT=(SEL==0)?tmp1:((SEL==1)?tmp2:((SEL==2)?BBUS:ABUS));

architecture Behavioral of digital_clock is

-- component declaration before instantiation below

component clk_div

port (

 clk_50: in std_logic;

 clk_1s : out std_logic

 );

end component;

signal clk, clk_1s: std_logic;

begin

-- component instantiation

create_1s_clock: clk_div port map (clk_50 => clk, clk_1s => clk_1s); 

end

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

package clock_div_pack is 

component clk_div is

 port (

         clk_50: in std_logic;

         clk_1s : out std_logic

 );

end component clk_div;

end package;

-- Declare the component in a separate package and 

-- reuse by using the following statement:

use work.clock_div_pack.all;

entity clock is

end clock;

architecture Behavioral of clock is

signal clk, clk_1s: std_logic;

begin

create_1s_clock: clk_div port map (clk_50 => clk, clk_1s => clk_1s); 

end

create_1s_clock: entity work.clk_div port map (clk_50 => clk, clk_1s => clk_1s);

type FSM is (IDLE, TEST, VERILOGvsVHDL, STOP, FPGA4student);

-- enumerated type

type int_4 is range 0 to 15;

-- record tye in VHDL

type record_example is record

 data1: integer;

 data2: int_4;

 data3: FSM;

end record;