新手园地

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AHB slave ·1 slave hb middot 卡拉瓦乔 2018-9-9 11:30 0 550
AHB-2 hb AN ADDR 怎么叫都可以 2018-9-9 11:28 0 156
AHB， Master will send start address 0x01 in real system？ address se System 向日葵的武士 2018-9-9 11:26 0 253
Partial Word Access to Altera Avalon Memory-Mapped Slave access slave Partial 博斯 2018-9-9 11:24 0 336
Configuration options for cxapbic for 32 masters and 2 slaves FOR Master OPTION 一片混沌 2018-9-9 11:22 0 335
In AMBA AHB Amba hb AN 3月的尾巴 2018-9-9 11:20 0 316
AHB HREADY low not after address phase hb address After 你画我瞎 2018-9-9 11:18 0 446
In AHB 2.0 Standard standard hb TE 电子学长 2018-9-9 11:16 0 326
why there is no split or retry responce in AXI ? ce INA 棋王高手 2018-9-9 11:14 0 394
Why the address boundary for AHB burst should not cross 1KB FOR Boundary hb 第三章 2018-9-9 11:12 0 230
Why does AHB or APB support only 16 slave devices? Devices hb slave 电员师 2018-9-9 11:10 0 389
STM(System Trace Macrocell) Trace System STM 小小的人呀 2018-9-9 11:08 0 438
Licensing FVP models models ICE RS 道子 2018-9-9 11:06 0 191
As the title says.. TI AN se roucun 2018-9-9 11:04 0 368
Not able to find the definition for GICD_IROUTERn register BLE CD ic 白鹭hu 2018-9-9 11:02 0 362
Not able to disable Affinity Routing BLE ni routing 电子学长 2018-9-9 11:00 0 279
GIC500 ic TI ST 你说说说说 2018-9-9 10:58 0 140
AXI INA LAN TI 无幻 2018-9-9 10:56 0 232
read transfers AD RS TRANSFER 一亚麻怡 2018-9-9 10:54 0 244
Cache Coherence Support in CHI Specification CACHE ce SPECIFICATION 奔跑的猫ちゃん 2018-9-9 10:52 0 328
Differences between Armv7 to Armv8? ARM between Differences 追光少年 2018-9-9 10:50 0 335
Old startup .s files from DS-1, etc. startup ROM 卡拉瓦乔 2018-9-9 10:48 0 230
Is it necessary to flush data cache 3 ce SAR CACHE 没名字的人 2018-9-9 10:46 0 236
Is it necessary to flush data cache 2 SAR NEC ce 小蘭 2018-9-9 10:44 0 255
Is it necessary to flush data cache 1 NEC CACHE SAR 冰糖炖雪梨 2018-9-9 10:42 0 290
Best way to safely check if virtual address exists Virtual AFE address kaloulin 2018-9-9 10:40 0 270
Protection control control protection AN 石头张 2018-9-9 10:38 0 460
CSAL on ARM A9 ARM ce ev 道子 2018-9-9 10:36 0 247
how to return from exception generated by SMC instruction ROM SMC return 稻花香1号 2018-9-9 10:34 0 256
[ArmV8] [Cortex-A53] [PMU] PM_CCNTR to measure cpuload PMU Measure cortex-A53 电员师 2018-9-9 10:32 0 381
Partial register dependency neon register pen Partial 河童 2018-9-9 10:30 0 296
How to do from Secure(EL3) Secure ROM TI kaloulin 2018-9-9 10:28 0 168
The "usage model" of ARMv8 SVE contiguous "non-fault" Fault Usage ARM 没名字的人 2018-9-9 10:26 0 359
ARM R5 and A53 cores coexist AN ST 第十代火影 2018-9-9 10:24 0 242
How to flush write buffer when memory attribute is normal_nc WRITE buffer memory 小小的人呀 2018-9-9 10:22 0 235
Address memory of the next instruction in A9 MPCore address nex 王将 2018-9-9 10:20 0 192
flush_cache_all() API consuming 200+ microseconds. CACHE Micro second 没名字的人 2018-9-9 10:18 0 272
Debug Connection Cause ExecutionTiming Problem BUG problem Cause 喷水壶 2018-9-9 10:16 0 335
Processor halt in __libc_init_array assembler function function ASSEMBLER ni 肉坨坨 2018-9-9 10:14 0 433
In Arm v7 mmu, stage2 translation cannot use short descriptors ARM Script short 石头张 2018-9-9 10:12 0 287