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Import SOC design in eclipse Design Eclipse IMPORT Spikess 2018-9-9 12:32 0 313
AHB protocol，what is meaning of single cycle bus master handover? AN Master protocol 博斯 2018-9-9 12:30 0 534
Sampling on positive edge of clock of slave in AXI3 edge ck Positive 冰糖炖雪梨 2018-9-9 12:28 0 500
Is there relation between the de-assertion of BVALID TI IO between 冷冻链 2018-9-9 12:26 0 503
Additional Control Information Questions additional information 3月的尾巴 2018-9-9 12:24 0 429
AMBA AXI reset？ Reset Amba ge kaloulin 2018-9-9 12:22 0 392
apb 2.0 continuous transfer TRANSFER continuous se 冰糖炖雪梨 2018-9-9 12:20 0 431
Alignment Address Calculation in AHB hb calculation address 丑帅丑帅的 2018-9-9 12:18 0 343
Any advice on running 180nm ROM/RAM compilers on modern Linux? Modern ni 肉坨坨 2018-9-9 12:16 0 399
apb protocol checker (assertions) se TI protocol 张さん 2018-9-9 12:14 0 463
Alignment Address Calculation in AHB hb calculation address 香菇选手 2018-9-9 12:12 0 588
Any advice on running 180nm ROM/RAM compilers on modern Linux? Modern ni Spikess 2018-9-9 12:10 0 485
apb protocol checker (assertions)? se TI protocol Spikess 2018-9-9 12:08 0 359
AXI4 Burst Transactions Actions ransac RS 奔跑的猫ちゃん 2018-9-9 12:06 0 506
Cycle Model Studio software Software Studio model 丑帅丑帅的 2018-9-9 12:04 0 296
What is Byte Invariance Variance TE ST 第三章 2018-9-9 12:02 0 254
When Wrapping happens in AXI? pen App pi 稻花香1号 2018-9-9 12:00 0 228
Is during AXI unaligned transfer not all WDATA bits used? TRANSFER se FOR 社畜一枚 2018-9-9 11:58 0 460
When should APB slave Sample address sample slave address 爱德华复制手 2018-9-9 11:56 0 408
[ARM GICv3 - GIC Stream protocol] ARM protocol stream 求关注啊 2018-9-9 11:54 0 355
Is there any scenario where HWDATA rio AN ce 社畜一枚 2018-9-9 11:52 0 248
What purpose does BURST feature in AHB serve? hb feature RS 河童 2018-9-9 11:50 0 408
多核与单核的编译一样么？编译丑帅丑帅的 2018-9-9 11:48 0 187
TEE对ArmV8 平台这样的多核环境的安全机制是怎样的？ ARM TE World 道子 2018-9-9 11:46 0 289
macOS Mojave 搭建 ARM 交叉编译环境 ARM 交叉编译环境 Macos 一亚麻怡 2018-9-9 11:44 0 692
Request for vendors: improve SPI/SSP request FOR RS 第8号打板工 2018-9-9 11:42 0 466
error when compiling ClockDiv_XilinxS6.v on Nexys3 kd ck Nexys3 roucun 2018-9-9 11:40 0 369
How can I get IP-XACT descriptions of CMSDK components? AC ge sdk 肉坨坨 2018-9-9 11:38 0 329
AHB Slave HREADY AD slave hb 冰糖炖雪梨 2018-9-9 11:36 0 224
AHB slave ·3 hb slave middot 博斯 2018-9-9 11:34 0 617
AHB slave ·2 hb slave middot 丑帅丑帅的 2018-9-9 11:32 0 585
AHB slave ·1 slave hb middot 卡拉瓦乔 2018-9-9 11:30 0 630
AHB-2 hb AN ADDR 怎么叫都可以 2018-9-9 11:28 0 222
AHB， Master will send start address 0x01 in real system？ address se System 向日葵的武士 2018-9-9 11:26 0 316
Partial Word Access to Altera Avalon Memory-Mapped Slave access slave Partial 博斯 2018-9-9 11:24 0 438
Configuration options for cxapbic for 32 masters and 2 slaves FOR Master OPTION 一片混沌 2018-9-9 11:22 0 410
In AMBA AHB Amba hb AN 3月的尾巴 2018-9-9 11:20 0 385
AHB HREADY low not after address phase hb address After 你画我瞎 2018-9-9 11:18 0 527
In AHB 2.0 Standard standard hb TE 电子学长 2018-9-9 11:16 0 381
why there is no split or retry responce in AXI ? ce INA 棋王高手 2018-9-9 11:14 0 485